MC100EPT21

MC100EPT21 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal. The VBB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 mF capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage r...