MC100H642

www.DataSheet4U.com MC10H642, MC100H642 68030/040 PECL to TTL Clock Driver Description The MC10H/100H642 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part−to−part skew, within−part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0 V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50 MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H642 also uses differential PECL internally to achieve its superior skew characteristic. The H642 includes divide−by−two and divide−by−four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz (see Logic Diagram). The 10H version is compatible with MECL 10H™ ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0 V). Features http://onsemi.com PLCC−28 FN SUFFIX CASE 776 MARKING DIAGRAM* 1 MCxxxH642G AWLYYWW Generates Clocks for 68030/040 Meets 030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and PECL Power/Ground Pins Asynchronous Reset Single +5.0 V Supply Pb−F...