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MC100H644 Dataheets PDF



Part Number MC100H644
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 68030/040 PECL-TTL CLOCK DRIVER
Datasheet MC100H644 DatasheetMC100H644 Datasheet (PDF)

www.DataSheet4U.com MC10H644, MC100H644 68030/040 PECL to TTL Clock Driver The MC10H/100H644 generates the necessary clocks for the 68030, 68040 and similar microprocessors. The device is functionally equivalent to the H640, but with fewer outputs in a smaller outline 20−lead PLCC package. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part−to−part skew, within−part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (E.

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www.DataSheet4U.com MC10H644, MC100H644 68030/040 PECL to TTL Clock Driver The MC10H/100H644 generates the necessary clocks for the 68030, 68040 and similar microprocessors. The device is functionally equivalent to the H640, but with fewer outputs in a smaller outline 20−lead PLCC package. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part−to−part skew, within−part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0 V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50 MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H644 also uses differential ECL internally to achieve its superior skew characteristic. The H644 includes divide−by−two and divide−by−four stages, both to achieve the necessary duty cycle and skew to generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz (see Logic Symbol). The 10H version is compatible with MECL™ 10H ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0 V). • Generates Clocks for 68030/040 • Meets 68030/040 Skew Requirements • TTL or PECL Input Clock • Extra TTL and ECL Power/Ground Pins • Within Device Skew on Similar Paths is 0.5 ns • Asynchronous Reset • Single +5.0 V Supply Function http://onsemi.com MARKING DIAGRAM 1 10H644 PLCC−20 FN SUFFIX CASE 775 AWLYYWW A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10H644FN MC100H644FN Package PLCC−20 PLCC−20 Shipping 37 Units/Rail 37 Units/Rail Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH. Synchronized Outputs: The device is designed to have the POS edges of the ÷2 and ÷4 outputs synchronized. Select (SEL): LOW selects the PECL input source (DE/DE). HIGH selects the TTL input source (DT). The H644 also contains circuitry to force a stable state of the PECL input differential pair, should both sides be left open. In this case, the DE side of the input is pulled LOW, and DE goes HIGH. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev. 6 1 Publication Order Number: MC10H644/D MC10H644, MC100H644 Q4 18 GT Q3 GT Q2 GT 19 20 1 2 3 4 Q1 5 VT 6 Q0 7 SEL 8 DT VT 17 Q5 16 GT 15 R 14 13 12 11 10 9 VE DE VBB DE GE Table 1. PIN DESCRIPTION PIN GT VT VE GE DE, DE VBB DT Qn, Qn SEL R FUNCTION TTL Ground (0 V) TTL VCC (+5.0 V) ECL VCC (+5.0 V) ECL Ground (0 V) ECL Signal Input (positive ECL) VBB Reference Output TTL Signal Input Signal Outputs (TTL) Input Select (TTL) Reset (TTL) *Skews are specified for Identical Edges Figure 1. Pinout: PLCC−20 (Top View) TTL OUTPUTS VBB DE (ECL) DE (ECL) 2:1 MUX ÷2 Q1 Q0 DT (TTL) Q2 SEL (TTL) ÷4 Q3 Q4 R (TTL) Q5 Figure 2. Logic Diagram http://onsemi.com 2 MC10H644, MC100H644 Table 2. 10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol IINH IINL VIH* VIL* VBB* Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage VE = 5.0 V VE = 5.0 V Condition Min 0.5 3.83 3.05 3.62 Max 255 4.16 3.52 3.73 25°C Min 0.5 3.87 3.05 3.65 Max 175 4.19 3.52 3.75 85°C Min 0.5 3.94 3.05 3.69 Max 175 4.28 3.55 3.81 Unit mA V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 3. 100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol IINH IINL VIH* VIL* VBB* Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage VE = 5.0 V VE = 5.0 V Condition Min 0.5 3.835 3.19 3.62 Max 255 4.12 3.525 3.74 25°C Min 0.5 3.835 3.19 3.62 Max 175 4.12 3.525 3.74 85°C Min 0.5 3.835 3.19 3.62 Max 175 4.12 3.525 3.74 Unit mA V V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. *PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0 V. Only corresponds to ECL Clock Inputs. Tabl.


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