MC100SX1230

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document from Logic Marketing Advance Information CMI Coder/Decoder The MC100SX1230 device consists of a Binary to CMI Coder and CMI to Binary Decoder with integrated loop back capability. The device is designed for CMI (Code Mark Inversion) interfaces in transmission applications supporting either 139.26 Mbit/s E4 or 155.52 Mbit/s STM1 line rates. MC100SX1230 Binary-to-CMI Coder and CMI-to-Binary Decoder Internal Loop Back Test Capability Supports SDH or PDH Applications Low Power Fully Differential 100K Compatible I/O VBB Reference Available 75kΩ Input Pulldown Resistors +5V PECL or –5V ECL Operation 28-Pin Surface Mount PLCC Package Asynchronous Reset CMI CODER/DECODER In normal operation, the coder and decoder operate independently. Both the coder and decoder operate from a 2X line rate clock. The device incorporates test circuitry to support loop back bypass so either the coder input can be routed to the decoder output or the decoder input can be routed to the coder output. The part is fabricated using Motorola’s proven MOSAIC III™ advanced bipolar process. The device provides a VBB output for accepting single-ended inputs. The VBB pin should only be used as a bias for the MC100SX1230 as its current sink/source capability is limited. Whenever used, the VBB pin should be bypassed to ground via a 0.01µF capacitor. CCLKout CCLKout QCMI QCMI QBIN 25 LCMI LBIN VEE VEE DCLKin DCLKin VBB 26 27 28 1 2 3...