MC10101

www.DataSheet4U.com MC10101 Quad OR/NOR Gate The MC10101 is a quad 2–input OR/NOR gate with one input from each gate common to pin 12. PD = 25 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM 4 7 10 13 12 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 2 5 3 6 14 11 15 9 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10101 AWLYYWW 16 MC10101P AWLYYWW CDIP–16 L SUFFIX CASE 620 1 http://onsemi.com MARKING DIAGRAMS 16 MC10101L AWLYYWW DIP PIN ASSIGNMENT A WL YY WW VCC1 AOUT BOUT AIN AOUT BOUT BIN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 DOUT COUT DIN COMMON INPUT COUT CIN DOUT = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10101L MC10101P MC10101FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2002 1 January, 2002 – Rev. 7 Publication Order Number: MC10101/D www.DataSheet4U.com MC10101 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 4 12 4 12 5 5 2 2 5 5 2 2 5 5 2 2 5 5 2 2 0.5 0.5 –1.060 –1.060 –1.060 –1.060 –1.890 –1.890 –1.890 –1.890 –1.080 –1.080 –1.080 –1.080 –1.655 –1.655 –1.655 –1.655 –0.890 –0.890 –0.890 –0.890 –1.675 –1.675 –1.675 –1.675 –30°C Min Max 29 425 850 0.5 0.5 –0.960 –0.960 –0.960 –0.960 –1.850 –1.850 –1.850 –1.85...