MC10109

MC10109 Dual 4-5-Input OR/NOR Gate The MC10109 is a dual 4–5 input OR/NOR gate. PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM ă4 ă5 ă6 ă7 ă9 10 11 12 13 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 3 2 CDIP–16 L SUFFIX CASE 620 1 14 15 PDIP–16 P SUFFIX CASE 648 1 1 PLCC–20 FN SUFFIX CASE 775 10109 AWLYYWW 16 MC10109P AWLYYWW http://onsemi.com MARKING DIAGRAMS 16 MC10109L AWLYYWW www.DataSheet4U.com DIP PIN ASSIGNMENT VCC1 AOUT AOUT AIN AIN AIN AIN VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 BOUT BOUT BIN BIN BIN BIN BIN A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10109L MC10109P MC10109FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2002 1 January, 2002 – Rev. 7 Publication Order Number: MC10109/D MC10109 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 4 4 2 3 2 3 2 3 2 3 0.5 –1.060 –1.060 –1.890 –1.890 –1.080 –1.080 –1.655 –1.655 –0.890 –0.890 –1.675 –1.675 –30°C Min Max 15 425 0.5 –0.960 –0.960 –1.850 –1.850 –0.980 –0.980 –1.630 –1.630 –0.810 –0.810 –1.650 –1.650 Min +25°C Typ 11 Max 14 265 0.3 –0.890 –0.890 –1.825 –1.825 –0.910 –0.910 –1.595 –1.595 –0.700 –0.700 –1.615 –1.615 Min +85°C Max 15 265 Unit mAdc µAdc µAdc ...