MC10111

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 3-Input/3-Output NOR Gate The MC10111 is designed to drive up to three transmission lines simul– taneously. The multiple outputs of this device also allow the wire “OR”–ing of several levels of gating for minimization of gate and package count. The ability to control three parallel lines from a single point makes the MC10111 particularly useful in clock distribution applications where minimum clock skew is desired. Three VCC pins are provided and each one should be used. MC10111 L SUFFIX CERAMIC PACKAGE CASE 620–10 PD = 80 mW typ/gate (No Load) tpd = 2.4 ns typ (All Outputs Loaded) tr, tf = 2.2 ns typ (20%–80%) P SUFFIX PLASTIC PACKAGE CASE 648–08 LOGIC DIAGRAM 2 5 6 7 3 4 12 9 10 11 13 14 DIP PIN ASSIGNMENT VCC1 AOUT AOUT AOUT AIN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 VCC1 BOUT BOUT BOUT BIN BIN BIN VCC1 = PIN 1,15 VCC2 = PIN 16 VEE = PIN 8 AIN AIN VEE Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D). 9/96 © Motorola, Inc. 1996 3–44 REV 6 MC10111 ELECTRICAL CHARACTERISTICS Test Limits Pin Pi Under Test 8 5, 6, 7 5, 6, 7 2 3 4 2 3 4 2 3 4 2 3 4 0.5 –1.060 –1.060 –1.060 –1.890 –1.890 –1.890 –1.080 –1.080 –1.080 –1.655 –1.655 –1.655 –0.890 –0.890 –0.890 –1.675 –1.675 –1.675 –30°C Min Max 42 680 0.5 –0.960 –0.960 –0.960 –1.850 –1.850 –1.850 –0.980 –0.980 –0.980 –1.630 –1.630 –1.630 –0.810 –0.810 –0.810 –1.650...