MC10113

MC10113 Quad Exclusive OR Gate The MC10113 is a quad Exclusive OR gate, with an enable common to all four gates. The outputs may be wire–ORed together to perform a 4–bit comparison function (A = B). The enable is active low. PD = 175 mW typ/pkg (No Load) tpd = 2.5 ns typ tr, tf = 2.0 ns typ (20%–80%) LOGIC DIAGRAM E 4 5 9 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 CDIP–16 L SUFFIX CASE 620 1 6 7 16 3 PDIP–16 P SUFFIX CASE 648 1 10 11 14 PLCC–20 FN SUFFIX CASE 775 1 10113 AWLYYWW MC10113P AWLYYWW http://onsemi.com MARKING DIAGRAMS 16 MC10113L AWLYYWW 2 12 13 15 VCC1 AOUT BOUT AIN AIN BIN BIN VEE DIP PIN ASSIGNMENT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 www.DataSheet4U.com VCC2 DOUT COUT DIN DIN CIN CIN ENABLE A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC10113L MC10113P MC10113FN Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). TRUTH TABLE IN L L H H X L H L H X E L L L L H OUTPUT L H H L L © Semiconductor Components Industries, LLC, 2002 1 January, 2002 – Rev. 7 Publication Order Number: MC10113/D MC10113 ELECTRICAL CHARACTERISTICS Test Limits Pin Under Test 8 4,7,10,13 5,6,11,12 9 * 2 3 14 15 2 3 14 15 2 3 14 15 2 3 14 15 0.5 –1.060 –1.060 –1.060 –1.060 –1.890 –1.890 –1.890 –1.890 –1.080 –1.080 –1.080 –1.080 –1.655 –...