MC10135

MC10135 Dual J-K Master-Slave Flip-Flop The MC10135 is a dual master–slave dc coupled J–K flip–flop. Asynchro– nous set (S) and reset (R) are provided. The set and reset inputs override the clock. A common clock is provided with separate J–K inputs. When the clock is static, the J–K inputs do not effect the output. The output states of the flip–flop change on the positive transition of the clock. PD = 280 mW typ/pkg (No Load) fTog = 140 MHz typ tpd = 3.0 ns typ tr, tf = 2.5 ns typ (20%–80%) DIP PIN ASSIGNMENT VCC1 Q1 Q1 R1 S1 K1 J1 VEE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q2 Q2 R2 S2 K2 J2 C S1 5 J1 7 K1 6 R1 4 C 9 S2 12 J2 10 K2 11 R2 13 www.DataSheet4U.com http://onsemi.com MARKING DIAGRAMS 16 CDIP–16 L SUFFIX CASE 620 1 16 MC10135L AWLYYWW LOGIC DIAGRAM Q1 Q1 2 3 PDIP–16 P SUFFIX CASE 648 1 MC10135P AWLYYWW 1 PLCC–20 FN SUFFIX CASE 775 10135 AWLYYWW Q2 15 14 Q2 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Package CDIP–16 PDIP–16 PLCC–20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail R–S TRUTH TABLE R L L H H S L H L H Qn+1 Qn H L N.D. CLOCK J–K TRUTH TABLE* J L H L H K L L H H Qn+1 Qn L H Qn MC10135L MC10135P MC10135FN N.D. = Not Defined * Output states change on positive transition of clock...