Document
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Bus Driver
The MC10192 contains four line drivers with complementary outputs. Each driver has a Data (D) input and shares an Enable (E) input with another driver. The two driver outputs are the uncommitted collectors of a pair of NPN transistors operating as a current switch. Each driver accepts 10K MECL input signals and provides a nominal signal swing of 800 mV across a 50 Ω load at each output collector. Outputs can drive higher values of load resistance, provided that the combination of IR drop and load return voltage VLR does not cause an output collector to go more negative than –2.4 V with respect to VCC. To avoid output transistor breakdown, the load return voltage should not be more positive than +5.5 V with respect to VCC. When the E input is high, both output transistors of a driver are nonconducting. When not used, the E inputs, as well as the D inputs, may be left open. Open Collector Outputs Drive Terminated Lines or Transformers 50 kΩ Input Pulldown Resistors on All Inputs (Unused Inputs May Be Left Open) Power Dissipation = 575 mW typ/pkg (No Load) Propagation Delay= 3.5 ns typ (E — Output) 3.0 ns typ (D — Output)
MC10192
L SUFFIX CERAMIC PACKAGE CASE 620–10 P SUFFIX PLASTIC PACKAGE CASE 648–08 FN SUFFIX PLCC CASE 775–02
DIP PIN ASSIGNMENT LOGIC DIAGRAM
E1 7 D1 5 3 4 1 D2 6 D3 10 2 Z1 Z1 Z2 Z1 Z2 D1 D2 E1 VEE 4 5 6 7 8 13 12 11 10 9 Z4 Z4 D4 D3 E2 Z2 Z2 Z1 1 2 3 16 15 14 VCC Z3 Z3
15 Z3 14 Z3
D4 11 E2 9
13 Z4 12 Z4 VCC = PIN 16 VEE = PIN 8
Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6–11 of the Motorola MECL Data Book (DL122/D).
TRUTH TABLE Inputs E H L L D X H L Z H H L Output Z H L H
Note: Unused outputs must be terminated to VCC for proper operation.
3/93
© Motorola, Inc. 1996
3–160
REV 5
MC10192
ELECTRICAL CHARACTERISTICS
Test Limits Pin Pi Under Test 8 5 5 2 2 2 2 2 13.5 13.3 5.5 –2.4 13.5 18.0 2.0 14.0 13.9 5.5 14.0 0.5 –30°C Min Max 154 350 0.5 2.0 18.0 2.0 14.0 13.3 5.5 14.0 19.0 2.0 Min +25°C Max 140 220 0.3 Min +85°C Max 154 220 Unit mAdc µAdc µAdc mAdc mAdc mAdc mAdc mAdc V V ns tPHL tPLH tTLH tTHL 2.0 1.5 6.0 4.5 3.3
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH IinL
Output Current High Output Current Low Threshold Current High Threshold Current Low Output Sink Current Low
Logic 1 Logic 0 Logic 1 Logic 0 Logic 0
IOH IOL IOHC IOLC IOS VLR VOLS
Load Return Voltage Absolute Max Rating (Note 1.) Output Voltage Low (Note 2.) Switching Times Propagation Delay Rise/Fall Time (50Ω Load) E to Output D to Output (20 to 80%)
1. The 5.5V value is a maximum rating, do not exceed. A 270Ω resistor will prevent output transistor breakdown. 2. Limitations of load resistor and load return voltage combinations. Refer to page 3–160 description.
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature –30°C +25°C +85°C Pin Under Test 8 5 5 2 2 2 5,10,11 2 5,6,10,11 5,6,10,11 5,7,9,10,11 7,9 6 6 5 5 5,6,10,11 VIHmax –0.890 –0.810 –0.700 VILmin –1.890 –1.850 –1.825 VIHAmin –1.205 –1.105 –1.035 VILAmax –1.500 –1.475 –1.440 VEE –5.2 –5.2 –5.2 (VCC) Gnd 16 16 16 16 16 16 16 16 16 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH IinL
Output Current High Output Current Low Threshold Current High Threshold Current Low Output Sink Current Low
Logic 1 Logic 0 Logic 1 Logic 0 Logic 0
IOH IOL IOHC IOLC IOS VLR VOLS
Load Return Voltage Absolute Max Rating (Note 1.) Output Voltage Low (Note 2.)
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
MECL Data DL122 — Rev 6
3–161
MOTOROLA
MC10192
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 775–02 ISSUE C
B –N– Y BRK D –L– –M– W D Z
0.007 (0.180) M T L–M U
S
N
S S
0.007 (0.180) M T L–M
N
S
20
1
X V VIEW D–D
G1
0.010 (0.250)
S
T L–M
S
N
S
A Z R
0.007 (0.180) M T L–M 0.007 (0.180) M T L–M
S
N N
S
S
S
H
0.007 (0.180) M T L–M
S
N
S
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L–M J –T–
SEATING PLANE
K1 K F VIEW S 0.007 (0.180)
M
VIEW S
S
T L–M
S
N
S
N
S
NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACK.