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MC10E150, MC100E150 5V ECL 6-Bit D Latch
Description
The MC10E/100E150 contains six D-type latches...
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MC10E150, MC100E150 5V ECL 6-Bit D Latch
Description
The MC10E/100E150 contains six D-type latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent and input data transitions propagate through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the data. The Master Reset (MR) overrides all other controls to set the Q outputs low. The 100 Series contains temperature compensation.
Features
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800 ps Max. Propagation Delay PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 50 kW Pulldown Resistors ESD Protection: Human Body Model; > 2 kV, Machine Model; > 200 V Charged Device Model; > 2 kV Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test Moisture Sensitivity Level: Pb = 1 Pb−Free = 3 For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34
Transistor Count = 173 devices Pb−Free Packages are Available*
PLCC−28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
MCxxxE150FNG AWLYYWW
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.
*For additional...