MC10H113

www.DataSheet4U.com MC10H113 Quad Exclusive OR Gate Description The MC10H113 is a Quad Exclusive OR Gate with an enable common to all four gates. The outputs may be wire−ORed together to perform a 4−bit comparison function (A = B). The enable is active LOW. Features http://onsemi.com MARKING DIAGRAMS* 16 MC10H113L AWLYYWW CDIP−16 L SUFFIX CASE 620A 1 Propagation Delay, 1.3 ns Typical Power Dissipation 175 mW Typ/Pkg (No Load) Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) Voltage Compensated MECL 10K™ Compatible Pb−Free Packages are Available* 16 16 1 PDIP−16 P SUFFIX CASE 648 1 MC10H113P AWLYYWWG 10H113 ALYWG SOEIAJ−16 CASE 966 1 20 20 1 PLLC−20 FN SUFFIX CASE 775 A WL, L YY, Y WW, W G 10H113G AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 8 1 Publication Order Number: MC10H113/D MC10H113 E 4 5 9 2 L L TRUTH TABLE IN L H L H X E OUTPUT L L L L L H H H L L 6 7 3 H H X VCC1 Aout Bout Ain Ain Bin Bin 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ...