MC10H117

www.DataSheet4U.com MC10H117 Dual 2−Wide 2−3−Input OR−AND/OR−AND Gate Description T h e M C 1 0 H 11 7 d u a l 2 − w i d e 2 − 3 − i n p u t O R − A N D / OR−AND−Invert gate is a general purpose logic element designed for use in data control, such as digital multiplexing or data distribution. Pin 9 is common to both gates. This MECL 10H™ part is a functional/pinout duplication of the standard MECL 10K™ family part, with 100% improvement in propagation delay, and no increase in power−supply current. Features http://onsemi.com MARKING DIAGRAMS* 16 MC10H117L AWLYYWW CDIP−16 L SUFFIX CASE 620A 1 Propagation Delay, 1.0 ns Typical Power Dissipation 100 mW/Gate Typical (same as MECL 10K) Improved Noise Margin 150 mV (Over Operating Voltage and Voltage Compensated MECL 10K Compatible Pb−Free Packages are Available* Temperature Range) 16 16 1 PDIP−16 P SUFFIX CASE 648 1 MC10H117P AWLYYWWG 10H117 ALYWG SOEIAJ−16 CASE 966 1 20 20 1 PLLC−20 FN SUFFIX CASE 775 A WL, L YY, Y WW, W G 10H117G AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. © Semiconductor Compone...