MC10H644

www.DataSheet4U.com MC10H644, MC100H644 68030/040 PECL to TTL Clock Driver The MC10H/100H644 generates the necessary clocks for the 68030, 68040 and similar microprocessors. The device is functionally equivalent to the H640, but with fewer outputs in a smaller outline 20−lead PLCC package. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part−to−part skew, within−part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0 V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50 MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H644 also uses differential ECL internally to achieve its superior skew characteristic. The H644 includes divide−by−two and divide−by−four stages, both to achieve the necessary duty cycle and skew to generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz (see Logic Symbol). The 10H version is compatible with MECL™ 10H ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0 V). Generates Clocks for 68030/040 Meets 68030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and ECL Power/Ground Pins Within Device Skew on Similar Paths is 0.5 ...