MC10LVELT22D

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual LVTTL/LVCMOS to Differential LVPECL Translator MC100LVELT22 The MC100LVELT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Low Voltage Positive ECL) levels are used, only +3.3V and ground are required. The small outline 8-lead SOIC package and the low skew, dual gate design of the LVELT22 makes it ideal for applications which require the translation of a clock and a data signal. 350ps Typical Propagation Delay <100ps Output–to–Output Skew Differential LVPECL Outputs Small Outline SOIC Package Flow Through Pinouts 8 1 D SUFFIX 8–LEAD PLASTIC SOIC PACKAGE CASE 751-05 LOGIC DIAGRAM AND PINOUT ASSIGNMENT Q0 1 8 VCC Q0 2 LVPECL LVTTL/ LVCMOS 7 D0 Q1 3 6 D1 PIN PIN DESCRIPTION FUNCTION Diff PECL Outputs LVTTL/LVCMOS Inputs +3.3V Supply Ground Q1 4 5 GND Qn Dn VCC GND 12/96 © Motorola, Inc. 1996 3–1 REV 0 MC100LVELT22 MAXIMUM RATINGS* Symbol VCC VIN IOUT TA TSTG Parameter DC Supply Voltage (Referenced to GND) Input Voltage Current Applied to Output in Low Output State Operating Temperature Range (In Free-Air) Storage Temperature Range Continuous Surge Value 7.0 0 to VCC 50 100 –40 to 85 –55 to +150 Unit V V mA °C °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. LVTTL/LVCMOS INPUT DC CHARACTERISTICS (VCC = 3.3V ±5%; TA = –40°C to 85°C) Symbol IIH IIHH IIL VIK...