Document
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14025B (see Page 6-5) MC14025UB (see Page 6-14)
MC14027B Dual J-K Flip-Flop
The MC14027B dual J–K flip–flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip–flop. These devices may be used in control, register, or toggle functions. • • • • Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Logic Swing Independent of Fanout Logic Edge–Clocked Flip–Flop Design — Logic state is retained indefinitely with clock level either high or low; information is transferred to the output only on the positive–going edge of the clock pulse • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4027B MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol VDD Parameter DC Supply Voltage L SUFFIX CERAMIC CASE 620
P SUFFIX PLASTIC CASE 648
ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ
Value Unit V V – 0.5 to + 18.0 ± 10 500 Vin, Vout lin, lout PD TL Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package† Storage Temperature mA mW Tstg – 65 to + 150 260
D SUFFIX SOIC CASE 751B
ORDERING INFORMATION
MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC
TA = – 55° to 125°C for all packages.
_C _C
BLOCK DIAGRAM
7 6 3 5 J C K R Q 2 S Q 1
Lead Temperature (8–Second Soldering)
* Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
Inputs C† J 1 X 0 X 1 X X X X X X X K X 0 X 1 1 X X X X S 0 0 0 0 0 0 1 0 1 R 0 0 0 0 0 0 0 1 Qn‡ 0 1 0 1 Qo X X X Outputs* Qn+1 1 1 0 0 Qo Qn 1 0 1 Qn+1 0 0 1 1 Qo Qn 0 1 1 No Change
4 9 10 13 11 12 VDD = PIN 16 VSS = PIN 8 J C K R Q 14 S Q 15
X = Don’t Care † = Level Change
1 X ‡ = Present State * = Next State
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
REV 3 1/94
©MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA
MC14027B 107
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