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MC14070B Dataheets PDF



Part Number MC14070B
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description CMOS SSI
Datasheet MC14070B DatasheetMC14070B Datasheet (PDF)

MC14070B, MC14077B CMOS SSI Quad Exclusive “OR” and “NOR” Gates The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. http://onsemi.com MARKING DIAGRAMS 14 PDIP–14 P SUFFIX CASE 646 MC140XXBCP AWLYYWW 1 14 SOIC–14 D SUFFIX CASE 751A 1 140XXB AWLYW.

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MC14070B, MC14077B CMOS SSI Quad Exclusive “OR” and “NOR” Gates The MC14070B quad exclusive OR gate and the MC14077B quad exclusive NOR gate are constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. These complementary MOS logic gates find primary use where low power dissipation and/or high noise immunity is desired. http://onsemi.com MARKING DIAGRAMS 14 PDIP–14 P SUFFIX CASE 646 MC140XXBCP AWLYYWW 1 14 SOIC–14 D SUFFIX CASE 751A 1 140XXB AWLYWW • Supply Voltage Range = 3.0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low–Power TTL Loads or One Low–Power • • • Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs MC14070B — Replacement for CD4030B and CD4070B Types MC14077B — Replacement for CD4077B Type MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8–Second Soldering) Value – 0.5 to +18.0 – 0.5 to VDD + 0.5 ± 10 500 – 55 to +125 – 65 to +150 260 Unit V V mA mW °C °C °C SOEIAJ–14 F SUFFIX CASE 965 14 MC140XXB AWLYWW 1 XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device MC140XXBCP MC140XXBD MC140XXBDR2 MC140XXBF MC140XXBFEL Package PDIP–14 SOIC–14 SOIC–14 SOEIAJ–14 SOEIAJ–14 Shipping 2000/Box 2750/Box 2500/Tape & Reel See Note 1. See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. © Semiconductor Components Industries, LLC, 2000 1 March, 2000 – Rev. 3 Publication Order Number: MC14070B/D MC14070B, MC14077B PIN ASSIGNMENT IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C MC14070B QUAD Exclusive OR Gate 1 3 2 5 4 6 8 10 9 12 11 13 MC14077B QUAD Exclusive NOR Gate 1 3 2 5 4 6 8 10 9 12 11 13 VDD = PIN 14 VSS = PIN 7 (BOTH DEVICES) 20 ns VDD IDD Vin * CL Vin 90% 50% 10% 20 ns VDD VSS 1/f 50% DUTY CYCLE *Inverted output on MC14077B only. Figure 1. Power Dissipation Test Circuit .


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