Document
M29F002T, M29F002NT M29F002B
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
5V ± 10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 70ns FAST PROGRAMMING TIME: 10µs typical PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte – Status Register bits MEMORY BLOCKS – Boot Block (Top or Bottom location) – Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI-BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend LOW POWER CONSUMPTION – Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code, M29F002T: B0h – Device Code, M29F002NT: B0h – Device Code, M29F002B: 34h DESCRIPTION The M29F002 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byte basis using only a single5V VCC supply.For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles.
July 1998
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N) 8 x 20mm
Figure 1. Logic Diagram
VCC
18 A0-A17 W E G (*) RPNC M29F002T M29F002B M29F002NT
8 DQ0-DQ7
VSS
AI02078C
Note: * RPNC function is not available for the M29F002NT
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M29F002T, M29F002NT, M29F002B
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
(*) RPNC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
AI02079C
1 32 2 31 3 30 4 29 5 28 6 27 7 26 M29F002T 8 25 M29F002B 9 M29F002NT24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI02080C
VCC W A17 A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A12 A15 A16 RPNC VCC W A17 1 32 A14 A13 A8 A9 A11 G A10 E DQ7 9 M29F002T M29F002B 25 17
Note: Pin 1 is not connected for the M29F002NT
Figure 2C. TSOP Pin Connections
Table 1. Signal Names
A0-A17 DQ0-DQ7 Address Inputs Data Input/Outputs, Command Inputs Chip Enable Output Enable Write Enable Reset / Block Temporary Unprotect Supply Voltage Ground
A11 A9 A8 A13 A14 A17 W VCC RPNC A16 A15 A12 A7 A6 A5 A4
1
32
8 9
M29F002T M29F002B
25 24
16
17
AI02361B
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
E G W RPNC (*) VCC VSS
DESCRIPTION (cont’d) Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commandsto a CommandInterfaceusing standard microprocessor write timings. The device is offered in PLCC32, PDIP32 and TSOP32 (8 x 20 mm) packages.
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M29F002T, M29F002NT, M29F002B
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO
(2)
Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage
(2) (3)
Value –40 to 125 –50 to 125 –65 to 150 –0.6 to 7 –0.6 to 7 –0.6 to 13.5
Unit °C °C °C V V V
VCC V(A9, E, G, RPNC)
A9, E, G, RPNC Voltage
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. 3. Depends on range.
Organisation The M29F002 is organised as 256K x 8. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. A Reset/Block Temporary Unprotection RPNC (NOT available on M29F002NT) tri-level input provides a hardwarereset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.).StatusRegister data outputon DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. Memory Blocks The devices feature asymmetrically blocked architecture providing system memory integration. The M29F002 has an array of 7 blocks, one Boot Block of 16 KBytes, two Parameter Blocks of 8 KBytes, one Main Block of 32 KBytes and three Main Blocks of 64 KBytes. The memory map is shown in Figure 3. Each b.