Flash Memory. M29F002BT Datasheet

M29F002BT Memory. Datasheet pdf. Equivalent

M29F002BT Datasheet
Recommendation M29F002BT Datasheet
Part M29F002BT
Description 2 Mbit 256Kb x8 / Boot Block Single Supply Flash Memory
Feature M29F002BT; M29F002BT M29F002BB, M29F002BNT 2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory PRELIMINARY.
Manufacture ST Microelectronics
Datasheet
Download M29F002BT Datasheet




ST Microelectronics M29F002BT
M29F002BT
M29F002BB, M29F002BNT
2 Mbit (256Kb x8, Boot Block) Single Supply Flash Memory
PRELIMINARY DATA
s SINGLE 5V ± 10% SUPPLY VOLTAGE for
PROGRAM, ERASE and READ OPERATIONS
s ACCESS TIME: 45ns
s PROGRAMMING TIME
– 8µs by Byte typical
s 7 MEMORY BLOCKS
– 1 Boot Block (Top or Bottom Location)
– 2 Parameter and 4 Main Blocks
s PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithm
– Embedded Multi-Block/Chip Erase algorithm
– Status Register Polling and Toggle Bits
s ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
s UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
s TEMPORARY BLOCK UNPROTECTION
MODE
s LOW POWER CONSUMPTION
– Standby and Automatic Standby
s 100,000 PROGRAM/ERASE CYCLES per
BLOCK
s 20 YEARS DATA RETENTION
– Defectivity below 1 ppm/year
s ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– M29F002BT Device Code: B0h
– M29F002BNT Device Code: B0h
– M29F002BB Device Code: 34h
PLCC32 (K)
TSOP32 (N)
8 x 20mm
32
1
PDIP32 (P)
Figure 1. Logic Diagram
VCC
18
A0-A17
8
DQ0-DQ7
W
M29F002BT
E M29F002BB
M29F002BNT
G
RP
VSS
AI02957
October 1999
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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ST Microelectronics M29F002BT
M29F002BT, M29F002BB, M29F002BNT
Figure 2A. PLCC Connections
Figure 2B. TSOP Connections
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
9
1 32
M29F002BT
M29F002BB
17
A14
A13
A8
A9
25 A11
G
A10
E
DQ7
AI02959
A11
A9
A8
A13
A14
A17
W
VCC
RP
A16
A15
A12
A7
A6
A5
A4
1 32
8 M29F002BT 25
9 M29F002BB 24
16 17
AI02958
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Figure 2C. PDIP Connections
RP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 M29F002BT 26
8 M29F002BB 25
9 M29F002BNT 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
W
A17
A14
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI02960
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Table 1. Signal Names
A0-A17
Address Inputs
DQ0-DQ7 Data Inputs/Outputs
E Chip Enable
G Output Enable
W Write Enable
M29F002BB, M29F002BT:
RP
Reset/Block Temporary Unprotect
M29F002NBT:
Not Connected Internally
VCC Supply Voltage
VSS Ground
SUMMARY DESCRIPTION
The M29F002B is a 2 Mbit (256Kb x8) non-volatile
memory that can be read, erased and repro-
grammed. These operations can be performed us-
ing a single 5V supply. On power-up the memory
defaults to its Read mode where it can be read in
the same way as a ROM or EPROM. The
M29F002B is fully backward compatible with the
M29F002.



ST Microelectronics M29F002BT
M29F002BT, M29F002BB, M29F002BNT
Table 2. Absolute Maximum Ratings (1)
Symbol
Parameter
Value
Unit
Ambient Operating Temperature (Temperature Range Option 1)
0 to 70
°C
TA Ambient Operating Temperature (Temperature Range Option 6) –40 to 85
°C
Ambient Operating Temperature (Temperature Range Option 3)
–40 to 125
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage
–0.6 to 6
V
VCC Supply Voltage
–0.6 to 6
V
VID Identification Voltage
–0.6 to 13.5
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Each block can
be protected independently to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The blocks in the memory are asymmetrically ar-
ranged, see Tables 3A and 3B, Block Addresses.
The first or last 64 Kbytes have been divided into
four additional blocks. The 16 Kbyte Boot Block
can be used for small initialization code to start the
microprocessor, the two 8 Kbyte Parameter
Blocks can be used for parameter storage and the
remaining 32K is a small Main Block where the ap-
plication may be stored.
Chip Enable, Output Enable and Write Enable sig-
nals control the bus operation of the memory.
They allow simple connection to most micropro-
cessors, often without additional logic.
The memory is offered in TSOP32 (8 x 20mm),
PLCC32 and PDIP packages. Access times of
45ns, 55ns, 70ns, 90ns and 120ns are available.
The memory is supplied with all the bits erased
(set to ’1’).
SIGNAL DESCRIPTIONS
See Figure 1, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A17). The Address Inputs
select the cells in the memory array to access dur-
ing Bus Read operations. During Bus Write opera-
tions they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data In-
puts/Outputs output the data stored at the selected
address during a Bus Read operation. During Bus
Write operations they represent the commands
sent to the Command Interface of the internal state
machine.
Chip Enable (E). The Chip Enable, E, activates
the memory, allowing Bus Read and Bus Write op-
erations to be performed. When Chip Enable is
High, VIH, all other pins are ignored.
Output Enable (G). The Output Enable, G, con-
trols the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Reset/Block Temporary Unprotect (RP). The Re-
set/Block Temporary Unprotect pin can be used to
apply a Hardware Reset to the memory or to tem-
porarily unprotect all blocks that have been pro-
tected. On the M29F002BNT the pin is not
connected internally and this feature is not avail-
able.
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