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M29F512B Dataheets PDF



Part Number M29F512B
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description 512 Kbit 64Kb x8 / Bulk Single Supply Flash Memory
Datasheet M29F512B DatasheetM29F512B Datasheet (PDF)

M29F512B 512 Kbit (64Kb x8, Bulk) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 45ns PROGRAMMING TIME – 8µs per Byte typical PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithm – Embedded Chip Erase algorithm – Status Register Polling and Toggle Bits TSOP32 (NZ) 8 x 14mm PLCC32 (K) s s s s UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming LOW POWER CONSUMPTION – Standby and Automatic St.

  M29F512B   M29F512B



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M29F512B 512 Kbit (64Kb x8, Bulk) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 45ns PROGRAMMING TIME – 8µs per Byte typical PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithm – Embedded Chip Erase algorithm – Status Register Polling and Toggle Bits TSOP32 (NZ) 8 x 14mm PLCC32 (K) s s s s UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming LOW POWER CONSUMPTION – Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES 20 YEARS DATA RETENTION – Defectivity below 1 ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 24h VCC s s s Figure 1. Logic Diagram s 16 A0-A15 W E G M29F512B 8 DQ0-DQ7 VSS AI02739 July 1999 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/16 M29F512B Figure 2A. TSOPConnections Figure 2B. PLCC Connections A11 A9 A8 A13 A14 NC W VCC NC NC A15 A12 A7 A6 A5 A4 1 32 8 9 M29F512B 25 24 16 17 AI02741 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 AI02930 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 A12 A15 NC NC VCC W NC 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 A14 A13 A8 A9 A11 G A10 E DQ7 9 M29F512B 25 17 Table 1. Signal Names A0-A15 DQ0-DQ7 E G W VCC VSS NC Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground Not Connected Internally quired to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP32 (8 x 14mm) and PLCC32 packages. Access times of 45ns and 70ns are available. The memory is supplied with all the bits erased (set to ’1’). SIGNAL DESCRIPTIONS See Figure 1, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A15). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. SUMMARY DESCRIPTION The M29F512B is a 512 Kbit (64Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re2/16 M29F512B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VID Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Identification Voltage Value 0 to 70 –50 to 125 –65 to 150 –0.6 to 6 –0.6 to 6 –0.6 to 13.5 Unit °C °C °C V V V Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be co.


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