M29F800AT

M29F800AT M29F800AB 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS ACCESS TIME: 70ns PROGRAMMING TIME – 8µs per Byte/Word typical 19 MEMORY BLOCKS – 1 Boot Block (Top or Bottom Location) – 2 Parameter and 16 Main Blocks 1 44 s s s s PROGRAM/ERASE CONTROLLER – Embedded Byte/Word Program algorithm – Embedded Multi-Block/Chip Erase algorithm – Status Register Polling and Toggle Bits – Ready/Busy Output Pin TSOP48 (N) 12 x 20mm SO44 (M) s ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend Figure 1. Logic Diagram s TEMPORARY BLOCK UNPROTECTION MODE LOW POWER CONSUMPTION – Standby and Automatic Standby 19 A0-A18 W E G RP VCC s 15 DQ0-DQ14 DQ15A–1 M29F800AT M29F800AB BYTE RB s 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1 ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – M29F800AT Device Code: 00ECh – M29F800AB Device Code: 0058h s s VSS AI02198B January 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/21 M29F800AT, M29F800AB Figure 2A. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 Figure 2B. SO Connections 12 13 M29F800A...