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M54HCT533 Dataheets PDF



Part Number M54HCT533
Manufacturers ST Microelectronics
Logo ST Microelectronics
Description OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT373 NON INVERTING - HCT533 INVERTING
Datasheet M54HCT533 DatasheetM54HCT533 Datasheet (PDF)

M54/74HCT373 M54/74HCT533 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT373 NON INVERTING - HCT533 INVERTING . . . . . . . HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8 V (MAX.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS373/533 B1R (Plastic Package) F1R (Ceramic P.

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M54/74HCT373 M54/74HCT533 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT HCT373 NON INVERTING - HCT533 INVERTING . . . . . . . HIGH SPEED tPD = 17 ns (TYP.) AT VCC = 5 V LOW POWER DISSIPATION ICC = 4 µA (MAX.) AT TA = 25 °C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8 V (MAX.) OUTPUT DRIVE CAPABILITY 15 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE IOL = IOH= 6 mA (MIN.) BALANCED PROPAGATION DELAYS tPLH = tPHL PIN AND FUNCTION COMPATIBLE WITH 54/74LS373/533 B1R (Plastic Package) F1R (Ceramic Package) M1R (Micro Package) C1R (Chip Carrier) DESCRIPTION The M54/74HCT373 and M54HCT533 are high speed CMOS OCTAL LATCH WITH 3-STATE OUTPUTS fabricated with in silicon gate C 2MOS technology. These ICs achive the high speed operation similar to equivalent LSTTL while maintaning the CMOS low power dissipation. These 8 bit D-Type latches are controlled by a latch enable input (LE) and a output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the OE input is at low level, the eight outputs will be in a normal logic state (high PIN CONNECTION (top view) HCT373 HCT533 ORDER CODES : M54HCTXXXF1R M74HCTXXXM1R M74HCTXXXB1R M74HCTXXXC1R or low logic level) and while high level the outpts will be in a high impedance state. The application designer has a choise of combination of inverting and non inverting outputs. The three state output configuration and the wide choise of outline make bus organized system simple. These integrated circuits have input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M54/74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption. All inputs are equipped with protection circuits against discharge and transient excess voltage. HCT373 HCT533 October 1993 1/13 M54/M74HCT373/533 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION (HCT373) PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND FUNCTION 3 State output Enable Input (Active LOW) 3 State outputs PIN DESCRIPTION (HCT533) PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 SYMBOL OE Q0 to Q7 NAME AND FUNCTION 3 State output Enable Input (Active LOW) 3 State outputs D0 to D7 Data Inputs D0 to D7 Data Inputs LE GND V CC Latch Enable Input Ground (0V) Positive Supply Voltage LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage IEC LOGIC SYMBOLS HCT373 HCT533 2/13 M54/M74HCT373/533 TRUTH TABLE INPUTS OE H L L L LE X L H H D X X L H Q (HCT373) Z NO CHANGE * L H OUTPUTS Q (HCT533) Z NO CHANGE * H L X: DON’T CARE Z: HIGH IMPEDANCE *: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL. LOGIC DIAG.


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