Document
M59MR032C M59MR032D
32 Mbit (2Mb x16, Mux I/O, Dual Bank, Burst) 1.8V Supply Flash Memory
s
SUPPLY VOLTAGE – VDD = VDDQ = 1.65V to 2.0V for Program, Erase and Read
s s
– VPP = 12V for fast Program (optional) MULTIPLEXED ADDRESS/DATA SYNCHRONOUS / ASYNCHRONOUS READ – Configurable Burst mode Read – Page mode Read (4 Words Page) – Random Access: 100ns
LFBGA54 (ZC) 10 x 4 ball array µBGA46 (GC) 10 x 4 ball array
BGA
µBGA
s
PROGRAMMING TIME – 10µs by Word typical – Double Word Programming Option
s
MEMORY BLOCKS – Dual Bank Memory Array: 8 Mbit - 24 Mbit – Parameter Blocks (Top or Bottom location) Figure 1. Logic Diagram
s
DUAL BANK OPERATIONS – Read within one Bank while Program or Erase within the other – No delay between Read and Write operations
VDD VDDQ VPP 5 A16-A20 W E G RP WP L K M59MR032C M59MR032D BINV WAIT 16 ADQ0-ADQ15
s
BLOCK PROTECTION/UNPROTECTION – All Blocks protected at Power-up – Any combination of Blocks can be protected
s s s s
COMMON FLASH INTERFACE (CFI) 64 bit SECURITY CODE ERASE SUSPEND and RESUME MODES 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M59MR032C: A4h – Bottom Device Code, M59MR032D: A5h
s
VSS
AI90109
April 2001
1/49
M59MR032C, M59MR032D
Figure 2. LFBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
A
DU
DU
B
DU
DU
C
DU
DU
D
DU
DU
E
WAIT
VSS
K
VDD
W
VPP
A19
A17
F
VDDQ
A16
A20
L
BINV
RP
WP
A18
E
VSS
G
VSS
ADQ7
ADQ6
ADQ13
ADQ12
ADQ3
ADQ2
ADQ9
ADQ8
G
H
ADQ15
ADQ14
VSS
ADQ5
ADQ4
ADQ11
ADQ10
VDDQ
ADQ1
ADQ0
J
DU
DU
K
DU
DU
L
DU
DU
M
DU
DU
AI90110
2/49
M59MR032C, M59MR032D
Figure 3. µBGA Connections (Top view through package)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
DU
DU
B
DU
DU
C
WAIT
VSS
K
VDD
W
VPP
A19
A17
D
VDDQ
A16
A20
L
BINV
RP
WP
A18
E
VSS
E
VSS
ADQ7
ADQ6
ADQ13
ADQ12
ADQ3
ADQ2
ADQ9
ADQ8
G
F
ADQ15
ADQ14
VSS
ADQ5
ADQ4
ADQ11
ADQ10
VDDQ
ADQ1
ADQ0
G
DU
DU
H
DU
DU
AI90111
3/49
M59MR032C, M59MR032D
Table 1. Signal Names
A16-A20 ADQ0-ADQ15 E G W RP WP K L WAIT BINV VDD VDDQ VPP VSS DU Address Inputs Data Input/Outputs or Address Inputs, Command Inputs Chip Enable Output Enable Write Enable Reset/Power-down Write Protect Burst Clock Latch Enable Wait Data in Burst Mode Bus Invert Supply Voltage Supply Voltage for Input/Output Buffers Optional Supply Voltage for Fast Program & Erase Ground Don’t Use as Internally Connected
DESCRIPTION The M59MR032 is a 32 Mbit non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-byWord basis using a 1.65V to 2.0V V DD supply for the circuitry. For Program and Erase operations the necessary high voltages are generated internally. The device supports synchronous burst read and asynchronous page mode read from all the blocks of the memory array; at power-up the device is configured for page mode read. In synchronous burst mode, a new data is output at each clock cycle for frequencies up to 54MHz. The array matrix organization allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power-up. Blocks can be unprotected to make changes in the application and then reprotected. Instructions for Read/Reset, Auto Select, Write Configuration Register, Programming, Block Erase, Bank Erase, Erase Suspend, Erase Resume, Block Protect, Block Unprotect, Block Locking, CFI Query, are written to the memory through a Command Interface (C.I.) using standard microprocessor write timings. The memory is offered in LFBGA54 and µBGA46, 0.5 mm ball pitch packages and it is supplied with all the bits erased (set to ’1’).
Table 2. Absolute Maximum Ratings (1)
Symbol TA TBIAS TSTG VIO (3) VDD, VDDQ VPP Parameter Ambient Operating Temperature (2) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage Program Voltage Value –40 to 85 –40 to 125 –55 to 155 –0.5 to VDDQ+0.5 –0.5 to 2.7 –0.5 to 13 Unit °C °C °C V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. 3. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
4/49
M59MR032C, M59MR032D
Organization The M59MR032 is organized as 2Mbit by 16 bits. The first sixteen address lines are multiplexed with the Data Input/Output signals on the multiplexed address/data bus ADQ0-ADQ15. The remaining address lines A16-A2.