M5M44405CJ

MITSUBISHI MITSUBISHI LSIs LSIs M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S EDO EDO ( HYPER ( HYPER PAGE PAGE MODE MODE ) 4194304-BIT ) 4194304-BIT ( 1048576-WORD ( 1048576-WORD BY BY 4-BIT 4-BIT ) DYNAMIC ) DYNAMIC RAM RAM DESCRIPTION This is a family of 1048576-word by 4-bit dynamic RAMs, fabricated with the high performance CMOS process,and is ideal for largecapacity memory systems where high speed, low power dissipation, and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. PIN CONFIGURATION (TOP VIEW) DQ1 1 DQ2 2 W 3 RAS 4 A9 5 26 VSS 25 DQ4 24 DQ3 23 CAS 22 OE FEATURES A0 9 18 A8 17 A7 16 A6 15 A5 14 A4 Type name M5M44405CXX-5,-5S M5M44405CXX-6,-6S M5M44405CXX-7,-7S RAS CAS access access time time (max.ns) (max.ns) Address OE Cycle Power access access time dissipatime time tion (max.ns) (max.ns) (min.ns) (typ.mW) A1 10 A2 11 A3 12 VCC 13 50 60 70 13 15 20 25 30 35 13 15 20 90 110 130 500 400 350 XX=J,TP Outline 26P0J (300mil SOJ) Standard 26 pin SOJ, 26 pin TSOP(II) Single 5V±10%supply Low stand-by power dissipation CMOS lnput level 5.5mW (Max) * CMOS lnput level 550µW (Max) Low operating powe...