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M5M5256DRV-70VLL-I Dataheets PDF



Part Number M5M5256DRV-70VLL-I
Manufacturers Mitsubishi
Logo Mitsubishi
Description 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Datasheet M5M5256DRV-70VLL-I DatasheetM5M5256DRV-70VLL-I Datasheet (PDF)

'97.4.7 MITSUBISHI LSIs M5M5256DFP,VP,RV -70VLL-I,-85VLL-I, -70VXL-I,-85VXL-I 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the m.

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'97.4.7 MITSUBISHI LSIs M5M5256DFP,VP,RV -70VLL-I,-85VLL-I, -70VXL-I,-85VXL-I 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5256DFP,VP,RV is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. Especially the M5M5256DVP,RV are packaged in a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board. PIN CONFIGURATION (TOP VIEW) A14 A12 1 2 A7 3 A6 4 A5 5 A4 6 7 A3 A2 8 A1 9 A0 10 DQ1 11 DQ2 12 DQ3 13 GND 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /W A13 A8 A9 A11 /OE A10 /S DQ8 DQ7 DQ6 DQ5 DQ4 M5M5256DFP -I FEATURE Type Access Power supply current time Active Stand-by (max) (max) (max) 70ns 24µA M5M5256DFP,VP,RV-85VLL 85ns 25mA (Vcc=3.6V) (Vcc=3.6V) Outline 28P2W-C (DFP) 22 /OE 23 A11 24 A9 25 A8 26 A13 27 /W 28Vcc 1 A14 2 A12 3 A7 4 A6 5 A5 6 A4 7 A3 A10 21 /S 20 DQ8 19 DQ7 18 DQ6 17 DQ5 16 DQ415 GND 14 DQ3 13 DQ2 12 DQ1 11 A0 10 A1 9 A2 8 M5M5256DFP,VP,RV-70VLL M5M5256DFP,VP,RV-70VXL M5M5256DFP,VP,RV-85VXL 70ns 85ns 4.8µA (Vcc=3.6V) 0.05µA (Vcc=3.0V, Typical) M5M5256DVP -I •Single +3.3±0.3V power supply •No clocks, no refresh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •/OE prevents data contention in the I/O bus •Common Data I/O •Battery backup capability •Low stand-by current··········0.05µA(typ.) Outline 28P2C-A (DVP) PACKAGE M5M5256DFP : 28 pin 450 mil SOP M5M5256DVP,RV : 28pin 8 X 13.4 mm2 TSOP APPLICATION Small capacity memory units 7 A3 6 A4 5 A5 4 A6 3 A7 2 A12 1 A14 28 Vcc 27 /W 26 A13 25 A8 24 A9 23 A11 22 /OE M5M5256DRV -I A2 8 A1 9 A0 10 DQ1 11 DQ2 12 DQ3 13 GND 14 DQ4 15 DQ5 16 DQ6 17 DQ7 18 DQ8 19 /S 20 A10 21 Outline 28P2C-B (DRV) MITSUBISHI ELECTRIC 1 '97.4.7 MITSUBISHI LSIs M5M5256DFP,VP,RV -70VLL-I,-85VLL-I, -70VXL-I,-85VXL-I 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5256DP,KP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable /OE directly controls the output stage. Setting the /OE at a high level,the output stage is i.


M5M5256DRV-70VLL M5M5256DRV-70VLL-I M5M5256DRV-70VLL-W


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