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M5M5256VP-55LL Dataheets PDF



Part Number M5M5256VP-55LL
Manufacturers Mitsubishi
Logo Mitsubishi
Description 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Datasheet M5M5256VP-55LL DatasheetM5M5256VP-55LL Datasheet (PDF)

'97.4.7 MITSUBISHI LSIs M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5256DP,FP,VP,RV is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for t.

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'97.4.7 MITSUBISHI LSIs M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5256DP,FP,VP,RV is 262,144-bit CMOS static RAMs organized as 32,768-words by 8-bits which is fabricated using high-performance 3 polysilicon CMOS technology. The use of resistive load NMOS cells and CMOS periphery results in a high density and low power static RAM. Stand-by current is small enough for battery back-up application. It is ideal for the memory systems which require simple interface. Especially the M5M5256DVP,RV are packaged in a 28-pin thin small outline package.Two types of devices are available, M5M5256DVP(normal lead bend type package), M5M5256DRV(reverse lead bend type package). Using both types of devices, it becomes very easy to design a printed circuit board. PIN CONFIGURATION (TOP VIEW) A14 A12 1 2 A7 3 A6 4 A5 5 A4 6 7 A3 A2 8 A1 9 A0 10 DQ1 11 DQ2 12 DQ3 13 GND 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc /W A13 A8 A9 A11 /OE A10 /S DQ8 DQ7 DQ6 DQ5 DQ4 M5M5256DP,FP FEATURE Type Access Power supply current time Active Stand-by (max) (max) (max) 45ns 55ns 70ns 45ns 55ns 70ns 55mA (Vcc=5.5V) Outline 28P4 (DP) 28P2W-C (DFP) M5M5256DP, FP,VP,RV-45LL M5M5256DP, FP,VP,RV-55LL M5M5256DP, FP,VP,RV-70LL M5M5256DP, FP,VP,RV-45XL M5M5256DP, FP,VP,RV-55XL M5M5256DP, FP,VP,RV-70XL 20µA (Vcc=5.5V) 5µA (Vcc=5.5V) 0.05µA (Vcc=3.0V, Typical) •Single +5V power supply •No clocks, no refresh •Data-Hold on +2.0V power supply •Directly TTL compatible : all inputs and outputs •Three-state outputs : OR-tie capability •/OE prevents data contention in the I/O bus •Common Data I/O •Battery backup capability •Low stand-by current··········0.05µA(typ.) 22 /OE 23 A11 24 A9 25 A8 26 A13 27 /W 28Vcc 1 A14 2 A12 3 A7 4 A6 5 A5 6 A4 7 A3 M5M5256DVP A10 21 /S 20 DQ8 19 DQ7 18 DQ6 17 DQ5 16 DQ415 GND 14 DQ3 13 DQ2 12 DQ1 11 A0 10 A1 9 A2 8 Outline 28P2C-A (DVP) 7 A3 6 A4 5 A5 4 A6 3 A7 2 A12 1 A14 28 Vcc 27 /W 26 A13 25 A8 24 A9 23 A11 22 /OE A2 8 A1 9 A0 10 DQ1 11 DQ2 12 DQ3 13 GND 14 DQ4 15 DQ5 16 DQ6 17 DQ7 18 DQ8 19 /S 20 A10 21 PACKAGE M5M256DP : 28 pin 600 mil DIP M5M5256DFP : 28 pin 450 mil SOP M5M5256DVP,RV : 28pin 8 X 13.4 mm2 M5M5256DRV TSOP APPLICATION Small capacity memory units Outline 28P2C-B (DRV) MITSUBISHI ELECTRIC 1 '97.4.7 MITSUBISHI LSIs M5M5256DP,FP,VP,RV -45LL,-55LL,-70LL, -45XL,-55XL,-70XL 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM FUNCTION The operation mode of the M5M5256DP,FP,VP,RV is determined by a combination of the device control inputs /S, /W and /OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level /W overlaps with the low level /S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of /W, /S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enab.


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