M5M54R04AJ-12

MITSUBISHI LSIs 1998.11.30 Ver.B PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M54R04AJ-10,-12,-15 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M54R04AJ is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS A0 1 A1 2 application. A2 3 address inputs A3 4 These devices operate on a single 3.3V supply, and are A 4 5 select directly TTL compatible. They include a power down chip input S 6 data inputs/ DQ 1 7 feature as well. outputs(3.3V) VCC 8 (0V) GND 9 FEATURES data inputs/ Fast access time M5M54R04AJ-10 ... 10ns(max) DQ2 10 outputs M5M54R04AJ-12 ... 12ns(max) write control W 11 input M5M54R04AJ-15 ... 15ns(max) A5 12 A6 13 Single +3.3V power supply address A7 14 inputs Fully static operation : No clocks, No refresh A8 15 Common data I/O A9 16 Easy memory expansion by S Three-state outputs : OR-tie capability Outline OE prevents data contention in the I/O bus Directly TTL compatible : All inputs and outputs silicon gate process and designed for high speed 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 address inputs A16 A15 output enable OE input DQ4 data inputs/ GND (0V) outputs VCC (3.3V) DQ3 data inputs/ outputs A14 A13 address A12 inputs A11 A10 NC 32P0K(SOJ) APPLICATION High-speed memory units PACKAGE M5M54R04AJ : 32pin 400mil SOJ BLOCK DIAGRAM A0 A1 A2 A3 adress inputs 1 2 3 4 MEMORY ARRAY 102...