M5M54R04J-15

MITSUBISHI LSIs M5M54R04J-12,-15 1997.11.20 Rev.F 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R04J is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS silicon gate PIN CONFIGURATION (TOP VIEW) A0 1 A1 2 address A2 3 lead package(SOJ). inputs A3 4 These device operate on a single 5V supply, and are directly A4 5 chip select TTL compatible. They include a power down feature as well. S 6 input data inputs/ DQ1 7 FEATURES outputs (5V) VCC 8 Fast access time M5M54R04J-12 12ns(max) (0V) GND 9 M5M54R04J-15 15ns(max) data inputs/ DQ 2 10 Low power dissipation Active 450mW(typ) outputs W 11 write control Stand by 5mW(typ) input A5 12 Single +5V power supply A6 13 Fully static operation : No clocks, No refresh address A7 14 Common data I/O inputs A8 15 Easy memory expansion by S A9 16 Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Directly TTL compatible : All inputs and outputs Outline The M5M54R04J is offered in a 32-pin plastic small outline J- process and designed for high speed application. 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 address A17 inputs A16 A15 output enable OE input DQ 4 data inputs/ GND (0V) outputs VCC (5V) DQ 3 data inputs/ outputs A14 A13 address A12 inputs A11 A10 NC M5M54R04J 32P0K(SOJ) APPLICATION High-speed memory units PACKAGE 32pin 400mil SOJ BLOCK DIAGRAM A0 A1 A2 address input...