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M5M54R16AJ-10 Dataheets PDF



Part Number M5M54R16AJ-10
Manufacturers Mitsubishi
Logo Mitsubishi
Description 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM
Datasheet M5M54R16AJ-10 DatasheetM5M54R16AJ-10 Datasheet (PDF)

1998.11.30 Ver.B MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R16A is a family of 262144-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as .

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1998.11.30 Ver.B MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R16A is a family of 262144-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB. CHIP SELECT INPUT DATA INPUTS/ OUTPUTS ADDRESS INPUTS PIN CONFIGURATION (TOP VIEW) FEATURES •Fast access time M5M54R16AJ,ATP-10 ... 10ns(max) M5M54R16AJ,ATP-12 ... 12ns(max) M5M54R16AJ,ATP-15 ... 15ns(max) A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 •Single +3.3V power supply •Fully static operation : No clocks, No refresh •Common data I/O •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs •Separate control of lower and upper bytes by LB and UB GND DQ5 DATA DQ6 INPUTS/ DQ7 OUTPUTS DQ8 WRITE CONTROL INPUT W A5 A6 ADDRESS INPUTS A7 A8 A9 (3.3V) (0V) VCC A17 ADDRESS A16 INPUTS A15 OUTPUT OE ENABLE INPUT BYTE UB CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) VCC DQ12 DQ11 DQ10 DQ9 N.C A14 A13 A12 A11 A10 (3.3V) DATA INPUTS/ OUTPUTS ADDRESS INPUTS Outline 44P0K APPLICATION High-speed memory system PACKAGE M5M54R16AJ .......... 44pin 400mil SOJ M5M54R16ATP .......... 44pin 400mil TSOP(II) state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upperByte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. FUNCTION The operation mode of the M5M54R16A is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION TABLE S L L L L L L L L H W H H H L L L H X X OE L L L X X X H X X LB L H L L H L X H X UB L L H L L H X H X Mode Read cycle All Bytes Read cycle Upper Bytes Read cycle Lower Bytes Write cycle All Bytes Write cycle Upper Bytes Write cycle Lower Bytes Output disable Non selection DQ1~8 D OUT High-impedance D OUT D IN High-impedance D IN High-impedance High-impedance DQ9~16 D OUT D OUT High-impedance D IN D IN High-impedance High-impedance High-impedance Icc Active Active Active Active Active Active Active Stand by BLOCK DIAGRAM ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 S W OE UB LB 1 2 3 4 5 18 19 20 21 22 MEMORY ARRAY 1024 ROWS 4096 COLUMNS 7 8 9 10 13 14 15 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DATA INPUTS/ OUTPUTS CHIP SELECT INPUT WRITE CONTROL INPUT OUTPUT ENABLE INPUT UPPER BYTE CONTROL INPUT LOWER BYTE CONTROL INPUT 6 17 COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS COLUMN INPUT BUFFERS 29 30 31 32 35 36 37 38 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DATA INPUTS/ OUTPUTS 41 40 11 33 12 VCC (3.3V) 39 23 24 25 26 27 42 43 44 34 GND (0V) A10 A11A12 A13 A14 A15A16A17 ADDRESS INPUTS MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M54R16AJ,ATP-10,-12,-15 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM ABSOLUTE MAXIMUM RATINGS Symbol V cc VI VO Parameter Supply voltage Input voltage Output voltage .


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