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M5M564R16DJ-12 Dataheets PDF



Part Number M5M564R16DJ-12
Manufacturers Mitsubishi
Logo Mitsubishi
Description 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM
Datasheet M5M564R16DJ-12 DatasheetM5M564R16DJ-12 Datasheet (PDF)

1998.6.18 Ver.A MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M564R16D is a family of 65536-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as we.

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1998.6.18 Ver.A MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM DESCRIPTION The M5M564R16D is a family of 65536-word by 16-bit static RAMs, fabricated with the high performance CMOS process and designed for high speed application. These devices operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. In write and read cycles, the lower and upper bytes are able to be controled either togethe or separately by LB and UB. ADDRESS INPUTS CHIP SELECT INPUTS DATA INPUTS/ OUTPUTS PIN CONFIGURATION (TOP VIEW) FEATURES •Fast access time M5M564R16DJ,TP-10 ... 10ns(max) M5M564R16DJ,TP-12 ... 12ns(max) M5M564R16DJ,TP-15 ... 15ns(max) •Low power dissipation Active .................. 363mW(typ) •Single +3.3V power supply •Fully static operation : No clocks, No refresh •Common data I/O •Easy memory expansion by S •Three-state outputs : OR-tie capability •OE prevents data contention in the I/O bus •Directly TTL compatible : All inputs and outputs •Separate control of lower and upper bytes by LB and UB A0 A1 A2 A3 A4 S DQ1 DQ2 DQ3 DQ4 1 2 3 4 5 6 44 43 42 41 40 39 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (3.3V) VCC (0V) GND DATA INPUTS/ OUTPUTS WRITE CONTROL INPUT ADDRESS INPUTS A15 A14 ADDRESS INPUTS A13 OUTPUT OE INPUT ENABLE UB BYTE CONTROL LB INPUTS DQ16 DQ15 DATA INPUTS/ DQ14 OUTPUTS DQ13 GND (0V) M5M564R16DJ,TP VCC (3.3V) DQ12 DQ11 DQ10 DQ9 N.C A12 A11 A10 A9 N.C DATA INPUTS/ OUTPUTS DQ5 DQ6 DQ7 DQ8 W A5 A6 A7 A8 N.C ADDRESS INPUTS Outline 44P0K(J) 44P3W-H(TP) APPLICATION High-speed memory system PACKAGE M5M564R16DJ M5M564R16DTP : 44pin 400mil SOJ : 44pin 400mil TSOP(II) FUNCTION The operation mode of the M5M564R16D is determined by a combination of the device control inputs S, W, OE, LB, and UB. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with low level LB and/or low level UB and low level S. The address must be set-up before write cycle and must be stable during the entire cycle. The data is latched into a cell on the traling edge of W, LB, UB or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while LB and/or UB and S are in an active state. (LB and/or UB=L, S=L) When setting LB at a high level and other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enable, and lower-Byte are in a non-selectable mode. And when setting UB at a high level and other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enable, and upperByte are in a non-selectable mode. When setting LB and UB at a high level or S at high level, the chip is in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by LB, UB and S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M564R16DJ,TP-10,-12,-15 1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM FUNCTION TABLE S L L L L L L L L H W H H H L L L H X X OE L L L X X X H X X LB L H L L H L X H X UB L L H L L H X H X Mode Read cycle All Bytes Read cycle Upper Bytes Read cycle Lower Bytes Write cycle All Bytes Write cycle Upper Bytes Write cycle Lower Bytes Output disable Non selection DQ1~8 D OUT High-impedance D OUT DQ9~16 D OUT D OUT High-impedance D IN D IN High-impedance High-impedance High-impedance Icc Active Active Active Active Active Active Active Stand by D IN High-impedance D IN High-impedance High-impedance BLOCK DIAGRAM ADDRESS INPUTS A0 A1 A2 A3 A4 A5 A6 A7 A8 S W OE UB LB ROW INPUT BUFFERS 3 4 5 18 19 20 21 ROW ADDRESS DECODERS 1 2 18 512 2048 DATA INPUT BUFFERS MEMORY ARRAY 512 ROWS 2048 COLUMNS 7 8 9 10 13 14 15 16 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 OUTPUT BUFFERS DATA INPUTS/ OUTPUTS OUTPUT BUFFERS CHIP SELECT INPUTS WRITE CONTROL INPUT OUTPUT ENABLE INPUT UPPER BYTE CONTROL INPUTS LOWER BYTE CONTROL INPUTS 6 17 COLUMN I/O CIRCUITS COLUMN ADDRESS DECODERS 14 29 30 31 32 35 36 37 38 DQ 9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DATA INPUTS/ OUTPUTS 41 COLUMN INPUT BUFFERS DATA INPUT BUFFERS 11 33 12 34 40 VCC (3.3V) 39 24 25 26 27 42 43 44 GND (0V) A9 A10 A11 A12 A13 A14 A15 ADDRESS INPUTS MITSUBISHI ELECTRIC.


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