M5M5T5636UG-22

January 14, 2003 Rev.0.7 Preliminary Notice: This is not final specification. Some parametric limits are subject to change. DESCRIPTION The M5M5T5636UG is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5T5636UG operates on 2.5V power/ 1.8V I/O supply or a single 2.5V power supply and are 2.5V CMOS compatible. FEATURES Fully registered inputs and outputs for pipelined operation Fast clock speed: 250, 225, and 200 MHz Fast access time: 2.6, 2.8, 3.2 ns Single 2.5V -5% and +5% power supply VDD Separate VDDQ for 2.5V or 1.8V I/O Individual byte write (BWa# - BWd#) controls may be tied LOW Single Read/Write control pin (W#) CKE# pin to enable clock and suspend operations Internally self-timed, registers outputs eliminate the need to control G# Snooze mode (ZZ) for power down Linear or Interleaved Burst Modes Three chip enables for simple depth expansion JTAG boundary scan support MITSUBISHI LSIs M5M5T5636UG – 25,22,20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM APPLICATION High-end networking products that require high bandwidth, such as switches and routers. FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals i...