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M5M5V108CVP-10X Dataheets PDF



Part Number M5M5V108CVP-10X
Manufacturers Mitsubishi
Logo Mitsubishi
Description 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Datasheet M5M5V108CVP-10X DatasheetM5M5V108CVP-10X Datasheet (PDF)

MITSUBISHI LSIs M5M5V108CFP,VP,RV,KV,KR -70H, -10H, -70X, -10X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION The M5M5V108CFP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and i.

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MITSUBISHI LSIs M5M5V108CFP,VP,RV,KV,KR -70H, -10H, -70X, -10X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION The M5M5V108CFP,VP,RV,KV,KR are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for the battery back-up application. The M5M5V108CVP,RV,KV,KR are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD). Two types of devices are available. M5M5V108CVP,KV(normal lead bend type package), M5M5V108CRV,KR(reverse lead bend type package).Using both types of devices, it becomes very easy to design a printed circuit board. PIN CONFIGURATION (TOP VIEW) NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 GND 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ADDRESS INPUTS FEATURES Type name M5M5V108CFP,VP,RV,KV,KR-70H Access time (max) Power supply current DATA INPUTS/ OUTPUTS VCC Active stand-by (1MHz) (max) (max) VCC ADDRESS A15 INPUT CHIP SELECT S2 INPUT WRITE CONTROL W INPUT A13 A8 ADDRESS INPUTS A9 A11 OUTPUT ENABLE OE INPUT ADDRESS A10 INPUT CHIP SELECT S1 INPUT DQ8 DQ7 DQ6 DATA INPUTS/ DQ5 OUTPUTS DQ4 Outline 32P2M-A A11 A9 A8 A13 W S2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 70ns M5M5V108CFP,VP,RV,KV,KR-10H 100ns 2.7~3.6V 5mA 70ns M5M5V108CFP,VP,RV,KV,KR-70X M5M5V108CFP,VP,RV,KV,KR-10X 100ns 12µA 4.8µA Low stand-by current 0.1µA (typ.) Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by S1,S2 Data hold on +2V power supply Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M5V108CFP ············ 32pin 525mil SOP M5M5V108CVP,RV ············ 32pin 8 X 20 mm2 TSOP M5M5V108CKV,KR ············ 32pin 8 X 13.4 mm 2 TSOP M5M5V108CVP,KV 25 24 23 22 21 20 19 18 17 APPLICATION Small capacity memory units OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 Outline 32P3H-E(VP), 32P3K-B(KV) A4 A5 A6 A7 A12 A14 A16 NC VCC A15 S2 W A13 A8 A9 A11 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 M5M5V108CRV,KR 24 25 26 27 28 29 30 31 32 A3 A2 A1 A0 DQ1 DQ2 DQ3 GND DQ4 DQ5 DQ6 DQ7 DQ8 S1 A10 OE Outline 32P3H-F(RV), 32P3K-C(KR) NC : NO CONNECTION MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs M5M5V108CFP,VP,RV,KV,KR -70H, -10H, -70X, -10X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M5V108C series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S 1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2, whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S 2 at a low level, the chip are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high- impedance state, allowing OR-tie with other chips and memory expansion by S1 and S2. The power supply current is reduced as low as the stand-by current which is specified as I CC3 or ICC4, and the memory data can be held at +2V power supply, enabling battery back-up operation during power failure or power-down operation in the nonselected mode. FUNCTION TABLE S1 X H L L L S2 L X H H H W X X L H H Mode DQ OE X Non selection High-impedance X Non selection High-impedance Din X Write Dout L Read High-impedance H ICC Stand-by Stand-by Active Active Active BLOCK DIAGRAM * A4 A5 A6 A7 8 7 6 5 16 15 14 13 12 11 10 7 4 * 21 22 13 DQ1 14 DQ2 15 DQ3 17 DQ4 18 DQ5 19 DQ6 20 DQ7 21 DQ8 DATA INPUTS/ OUTPUTS A12 4 A14 3 A16 2 A15 31 A13 28 131072 WORDS X 8 BITS ( 512 ROWS X128 COLUMNS X 16BLOCKS ) 23 25 26 27 28 29 ADDRESS INPUTS A0 12 A1 11 A2 10 A3 9 20 19 18 17 5 A10 23 A8 A9 27 26 31 3 2 1 32 8 24 30 6 WRITE 29 W CONTROL INPUT 22 S1 30 S2 CHIP SELECT INPUTS CLOCK GENERATOR A11 25 OUTPUT 24 OE ENABLE INPUT 32 VCC 16 GND (0V) * Pin numbers inside dotted line show those of TSOP MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs M5M5V108CFP,VP,RV,KV,KR -70H, -10H, -70X, -10X 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RA.


M5M5V108CVP-10HI M5M5V108CVP-10X M5M5V108CVP-10XI


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