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M5M5V108DVP-70H Dataheets PDF



Part Number M5M5V108DVP-70H
Manufacturers Mitsubishi
Logo Mitsubishi
Description 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
Datasheet M5M5V108DVP-70H DatasheetM5M5V108DVP-70H Datasheet (PDF)

7th.July.2000 Ver. 1.0 MITSUBISHI LSIs M5M5V108DFP,VP,KV -70H 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION The M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using highperformance triple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for th.

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7th.July.2000 Ver. 1.0 MITSUBISHI LSIs M5M5V108DFP,VP,KV -70H 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM DESCRIPTION The M5M5V108DFP,VP,KV are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using highperformance triple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM. They are low standby current and low operation current and ideal for the battery back-up application. The M5M5V108DVP,KV are packaged in a 32-pin thin small outline package which is a high reliability and high density surface mount device(SMD). PIN CONFIGURATION (TOP VIEW) ADDRESS INPUTS FEATURES Access time (max) Power supply current Type name M5M5V108DFP,VP,KV-70H VCC Active stand-by (1MHz) (max) (max) 70ns 2.7~3.6V 5mA 12µA DATA INPUTS/ OUTPUTS NC 1 A16 2 A14 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 DQ1 13 DQ2 14 DQ3 15 GND 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC ADDRESS A15 INPUT SELECT S2 CHIP INPUT WRITE CONTROL W INPUT A13 A8 ADDRESS INPUTS A9 A11 OUTPUT ENABLE OE INPUT A10 ADDRESS INPUT SELECT S1 CHIP INPUT DQ8 DQ7 DQ6 DATA INPUTS/ DQ5 OUTPUTS DQ4 Directly TTL compatible : All inputs and outputs Easy memory expansion and power down by S1,S2 Data hold on +2V power supply Three-state outputs : OR - tie capability OE prevents data contention in the I/O bus Common data I/O Package M5M5V108DFP ············ 32pin 525mil SOP 2 M5M5V108DVP,RV ············ 32pin 8 X 20 mm TSOP 2 M5M5V108DKV,KR ············ 32pin 8 X 13.4 mm TSOP A11 A9 A8 A13 W S2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 Outline 32P2M-A APPLICATION Small capacity memory units M5M5V108DVP,KV 25 24 23 22 21 20 19 18 17 OE A10 S1 DQ8 DQ7 DQ6 DQ5 DQ4 GND DQ3 DQ2 DQ1 A0 A1 A2 A3 Outline 32P3H-E(VP), 32P3K-B(KV) NC : NO CONNECTION MITSUBISHI ELECTRIC 1 7th.July.2000 Ver. 1.0 MITSUBISHI LSIs M5M5V108DFP,VP,KV -70H 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M5V108D series are determined by a combination of the device control inputs S1,S2,W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S 1 and the high level S2. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W,S1 or S2,whichever occurs first,requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while S1 and S2 are in an active state(S1=L,S2=H). When setting S1 at a high level or S 2 .


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