M5M5V4R08J-20

MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change M5M5V4R08J-12,-15,-20 1997.02.06 Rev.D 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM DESCRIPTION The M5M5V4R08J is a family of 524288-word by 8-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. The M5M5V4R08J is offered in a 36-pin plastic small outline J-lead package(SOJ). These device operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. PIN CONFIGURATION (TOP VIEW) FEATURES M5M5V4R08J-12 12ns(max) M5M5V4R08J-15 15ns(max) M5M5V4R08J-20 20ns(max) Low power dissipation Active 363mW(typ) Stand by 3.3mW(typ) Single +3.3V power supply Fully static operation : No clocks, No refresh Common data I/O Easy memory expansion by S Three-state outputs : OR-tie capability OE prevents data contention in the I/O bus Directly TTL compatible : All inputs and outputs Fast access time A0 A1 address A2 inputs A3 A4 chip select S input data inputs/ DQ1 outputs DQ2 (3.3V) VCC (0V) GND data DQ3 inputs/ DQ4 outputs write control W input A5 A6 address A7 inputs A8 A9 1 2 3 4 5 36 35 34 33 32 6 7 8 9 10 11 12 13 14 15 16 17 18 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 address inputs A16 A15 output enable OE input data DQ8 inputs/ DQ7 outputs GND (0V) VCC (3.3V) DQ6 data inputs/ DQ5 outputs...