256 x 9-BIT MAIL-BOX
MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66221SP/FP M66221SP/FP
× 9-BIT MAIL-BOX 256256 × 9-BIT MAIL-BOX
...
Description
MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66221SP/FP M66221SP/FP
× 9-BIT MAIL-BOX 256256 × 9-BIT MAIL-BOX
DESCRIPTION
The M66221 is a mail box that incorporates a complete CMOS shared memory cell of 256 × 9-bit configuration using high-performance silicon gate CMOS process technology, and is equipped with two access ports of A and B. Access ports A and B are equipped with independent addresses CS, WE and OE control pins and I/O pins to allow independent and asynchronous read/write operations from/to shared memory individually. This product also incorporates a port adjustment arbitration function in address contention from both ports.
PIN CONFIGURATION (Top view)
CHIP SELECT INPUT CSA → 1 WRITE ENABLE INPUT WEA → 2 NOT READY Not Ready A ← 3 OUTPUT OUTPUT ENABLE INPUT OEA → 4
48 VCC 47 ← CSB CHIP SELECT INPUT 46 ← WEB WRITE ENABLE INPUT READY 45 → Not Ready B NOT OUTPUT 44 ← OEB OUTPUT ENABLE INPUT 43 NC 42 ← A0B 41 ← A1B 40 ← A2B 39 ← A3B B PORT ADDRESS 38 ← A4B INPUT 37 ← A5B 36 ← A6B 35 ← A7B 34 NC 33 ↔ I/O8B 32 ↔ I/O7B 31 ↔ I/O6B 30 ↔ I/O5B B PORT 29 ↔ I/O4B DATA I/O 28 ↔ I/O3B 27 ↔ I/O2B 26 ↔ I/O1B 25 ↔ I/O0B
NC A PORT ADDRESS INPUT
5
A0A → 6 A1A → 7 A2A → 8 A3A → 9 A4A → 10 A5A → 11 A6A → 12 A7A → 13 NC 14
FEATURES
Memory configuration of 256 × 9 bits High-speed access, address access time 40ns (typ.) Complete asynchronous accessibility from ports A a...
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