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MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP ASSP 〉 〉
M66332FP M66332FP
FACSIMILE IMAGE DATA PROCESSOR FACSIMILE IMAGE DATA PROCESSOR
DESCRIPTION The M66332 is a facsimile image processing controller that converts analog signals that are photoelectrically converted by an image sensor into bi-level signals. It has image processing functions such as peak detection, uniformity correction, γ correction, MTF compensation, detector of background and object levels, dither control, separation of image data area, scale down, and area specification. This controller has a built-in 5-bit flash type A-D converter and interface circuits to image sensor, analog signal processing circuit, and CODEC (Coder & Decoder) to simplify control of the readout mechanism. FEATURES 0 High Speed Scan (MAX. 2 ms/line, TYP. 5 ms/line) 0 A3 (8 pixels/mm) Line Sensor Attachment 0 Image sensor (CCD,CIS) control signal generation CCD: SH, CK1, CK2, RS Contact sensor (CIS): SH, CK1 (or CK2)
0 Analog signal processing circuit control signal generation CLAMP, S/H, AGC, DSCH 0 Built-in 5-bit Flash Type A-D Converter 0 Bi-level data external input/output interface Serial output (→M66330) 8-bit MPU bus output with external DMA control signal 0 Image data processing γ correction Uniformity correction (block correction in units of 8 pixels) MTF compensation (1 dimension) Detector of background and object level (programmable) Dithering control • Dither method (16 levels using 4 × 4 matrix) Separation of image data area (1 dimension) Scale down A3 → B4, A3 → A4, B4 → A4 0 5V Single Power Supply APPLICATION Facsimiles
PIN CONFIGURATION (TOP VIEW)
D7 D6 D5 D4 MPU Interface D3 (DATA) D2 D1 D0 GND VCC A3 A2 MPU Interface A1 (ADDRESS) A0 DGND DVCC
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
GND VCC CS RD MPU Interface WR RESET GND GND DRQ DMA Interface DAK VCC SH Sensor Interface
29
45 46 47 48 49 50 51 52 53 54 55 56
M66332FP
28 27 26 25 24 23 22 21 20 19 18 17
TEST ASIG NC VWL VML3 VML2 GND VML1 VBL AGND AVCC DSCH
Test pin Analog Signal Processing Interface White Basic Supply Voltage Middle Basic Supply Voltage 3 Middle Basic Supply Voltage 2 Middle Basic Supply Voltage 1 Black Basic Supply Voltage
10
11
12
13
14
15
CK2 Sensor Interface CK1 RS Analog Signal CLAMP Prosessing S/H Interface GND Test pin TEST System clock SYSCK Test pin TEST VCC SVID CODEC SCLK Interface STIM SRDY Sensor Interface PTIM Analog Signal AGC Processing Interface
16
Analog Signal Processing Interface
1
2
3
4
5
6
7
8
9
NC: No Connection
Outline 56P6N-A
1
MITSUBISHI 〈DIGITAL ASSP〉
M66332FP
FACSIMILE IMAGE DATA PROCESSOR
BLOCK DIAGRAM
System Clock SYSCK 8 PTIM SH Sensor CK1 Interface CK2 RS Analog Signal Interface CLAMP S/H AGC DSCH 15 56 2 1 3 4 5 16 17 ADC Analog Vcc AVCC 18 ADC Logic Vcc DVCC 29
VCC 10 35 46 55
Image Processing Sequence Control Signal
Sensor Control To each block
Detection of Image Data Area
Separation of Image Data Area
Convert to bi-level
Cur out/ Scale down
14 13 12 11
SRDY STIM CODEC SCLK Interface SVID
Analog Control Correction memory (304 words × 5bits)
MTF compensation
Simple Bi-level Conversion/Background and object Level Detection
DMA Control
54 DAK DMA 53 DRQ Interface 50 47 48 49 31 RESET CS MPU Interface RD WR A0 MPU Interface 34 A3 (Address) 37 D0 MPU 44 D7 Interface (Data)
~ ~
Uniformity Correction
SRAM 16 words × 4bits
Collective Dithering (16 levels) MPU Bus Interface
ASIG 27
5bit A-D converter (flash type)
20 21 23 24 25 VBL VML2 VWL VML1 VML3 ADC Reference Voltage
19 AGND ADC Analog GND
30 6 22 36 45 51 52 DGND GND ADC Logic GND
Table 1 Image Processing Functions
Image Processing Function Read Width Resolution Read speed Uniformity Correction MTF Compensation Simple Bi-level Conversion Pseudo half-tone Separation of Image Data Area Scale down γ Correction Image Sensor Control Signal Analog Signal Processing Specifications • A4, B4, A3 • 8 pixels/mm (primary scanning direction) • 5ms/line Typ. 2ms/line maximum • White correction only • Block correction in units of 8 pixels • 50% Correction range • Laplacian filter circuit for 3 × 1 pixels in current line (1 dimension) • Floating threshold method using background and object level detection circuit • Dither method: 16 levels (4 × 4matrix) • Detection by brightness difference in 5 × 1 pixels area in current line • Selection method • Scale down: A3 → B4 set to 13/15; B4 → A4, 9/11; A3 → A4, 12/17 • Logarithmic correction • Control signal generation for contact sensor (CIS) and scale down CCD • Generate control signals for external CLAMP circuit, sample/hold circuit, and AGC circuit Remarks
• Operated with system clock and PRE_DATA (registers 2, 3) • Built-in SRAM as correction memory (304 words × 5bits) (read/write allowed from MPU) • No need for compensation memory
• Built-in SRAM as dither memory (16 words × 4bits) (read/write allowed from MPU) • No need for processing memory
• Apply external voltage (resistor connection is also allowed) t.