M68AR024D

M68AR024D 16 Mbit (1M x16) 1.8V Asynchronous SRAM PRELIMINARY DATA FEATURES SUMMARY s SUPPLY VOLTAGE: 1.65 to 1.95V s s s s s s s s Figure 1. Packages I/O SUPPLY VOLTAGE: 1.5 to 1.95V 1M WORDS x 16 bits LOW POWER SRAM EQUAL CYCLE and ACCESS TIME: 70ns LOW VCC DATA RETENTION: 1.0V LOW STANDBY CURRENT TRI-STATE COMMON I/O SINGLE BYTE READ/WRITE AUTOMATIC POWER DOWN TFBGA48 (ZH) 8 x 10 mm (for Engineering Samples only) BGA BGA TFBGA48 (ZB) 6.5 x 10 mm October 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/19 M68AR024D TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 2. Absolute Maxi...