TRANSPARENT LATCHES. IDT54FCT573CT Datasheet


IDT54FCT573CT LATCHES. Datasheet pdf. Equivalent


IDT54FCT573CT


FAST CMOS OCTAL TRANSPARENT LATCHES
Integrated Device Technology, Inc.

FAST CMOS OCTAL TRANSPARENT LATCHES

IDT54/74FCT373T/AT/CT/DT - 2373T/AT/CT IDT54/74FCT533T/AT/CT IDT54/74FCT573T/AT/CT/DT - 2573T/AT/CT

FEATURES:
• Common features: – Low input and output leakage ≤1µA (max.) – CMOS power levels – True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) – Meets or exceeds JEDEC standard 18 specifications – Product available in Radiation Tolerant and Radiation Enhanced versions – Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) – Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages • Features for FCT373T/FCT533T/FCT573T: – Std., A, C and D speed grades – High drive outputs (-15mA IOH, 48mA IOL) – Power off disable outputs permit “live insertion” • Features for FCT2373T/FCT2573T: – Std., A and C speed grades – Resistor output (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.)

– Reduced system switching noise

DESCRIPTION:
The FCT373T/FCT2373T, FCT533T and FCT573T/ FCT2573T are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When ...



IDT54FCT573CT
IDT54/74FCT573T/AT/CT
FASTCMOSOCTALTRANSPARENTLATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
FAST CMOS OCTAL
TRANSPARENT LATCH
IDT54/74FCT573T/AT/CT
FEATURES:
• Std., A, and C grades
• Low input and output leakage 1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
• Power off disable outputs permit "live insertion"
• Available in the following packages:
– Industrial: SOIC, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT573Tis an octal transparent latch built using an advanced dual
metal CMOS technology. These octal latches have 3-state outputs and are
intended for bus oriented applications. The flip-flops appear transparent to
the data when Latch Enable (LE) is high. When LE is low, the data that meets
the set-up time is latched. Data appears on the bus when the Output Enable
(OE) is low. When OE is high, the bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
D
O
G
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2016
DSC-5948/8

IDT54FCT573CT
IDT54/74FCT573T/AT/CT
FASTCMOSOCTALTRANSPARENTLATCH
PIN CONFIGURATION
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O0
18 O1
17 O2
16 O3
15 O4
14 O5
13 O6
12 O7
11 LE
MILITARYANDINDUSTRIALTEMPERATURERANGES
INDEX
32
20 19
D2 4
1 18 O1
D3 5
17 O2
D4 6
16 O3
D5 7
15 O4
D6 8
14 O5
9 10 11 12 13
CERDIP/ SOIC/ QSOP
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM(2)
VTERM(3)
TSTG
IOUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to VCC+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
COUT
Output Capacitance VOUT = 0V
8
12 pF
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Description
Dx DataInputs
LE Latch Enable Input (Active HIGH)
OE Output Enable Input (Active LOW)
O x 3-StateOutputs
FUNCTION TABLE(1)
Inputs
Dx LE
HH
LH
XX
OE
L
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
Outputs
Ox
H
L
Z
2




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)