PHB11N06LT

Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET FEATURES ’Trench’ technology Very low on-state resistance Fast switching Stable off-state characteristics High thermal cycling performance Low thermal resistance PHB11N06LT, PHD11N06LT SYMBOL d QUICK REFERENCE DATA VDSS = 55 V ID = 11 A g s RDS(ON) ≤ 150 mΩ (VGS = 5 V) RDS(ON) ≤ 130 mΩ (VGS = 10 V) GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHB11N06LT is supplied in the SOT404 surface mounting package. The PHD11N06LT is supplied in the SOT428 surface mounting package. PINNING PIN 1 2 3 tab gate drain 1 source DESCRIPTION SOT428 tab SOT404 tab 2 2 3 drain 1 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 ± 13 11 7.6 44 36 175 UNIT V V V A A A W ˚C 1 It is not possible to make contact to pin 2 of the SOT404 or SOT428 package September 1998 1...