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PHB27NQ10T Dataheets PDF



Part Number PHB27NQ10T
Manufacturers NXP
Logo NXP
Description N-channel TrenchMOS transistor
Datasheet PHB27NQ10T DatasheetPHB27NQ10T Datasheet (PDF)

Philips Semiconductors Product specification N-channel TrenchMOS™ transistor PHP27NQ10T, PHB27NQ10T PHD27NQ10T QUICK REFERENCE DATA d FEATURES • ’Trench’ technology • Low on-state resistance • Fast switching • Low thermal resistance SYMBOL VDSS = 100 V ID = 28 A g RDS(ON) ≤ 50 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:• d.c. to d.c. converters • switched mode power supplies The PHP27NQ10.

  PHB27NQ10T   PHB27NQ10T


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Philips Semiconductors Product specification N-channel TrenchMOS™ transistor PHP27NQ10T, PHB27NQ10T PHD27NQ10T QUICK REFERENCE DATA d FEATURES • ’Trench’ technology • Low on-state resistance • Fast switching • Low thermal resistance SYMBOL VDSS = 100 V ID = 28 A g RDS(ON) ≤ 50 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench’ technology. Applications:• d.c. to d.c. converters • switched mode power supplies The PHP27NQ10T is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB27NQ10T is supplied in the SOT404 (D2PAK) surface mounting package. The PHD27NQ10T is supplied in the SOT428 (DPAK) surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain 1 source SOT78 (TO220AB) tab SOT404 (D2PAK) tab SOT428 (DPAK) tab 2 1 23 2 1 3 1 3 drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 100 100 ± 20 28 20 112 107 175 UNIT V V V A A A W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages. August 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS™ transistor PHP27NQ10T, PHB27NQ10T PHD27NQ10T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 20 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig:15 MIN. MAX. 128 UNIT mJ IAS - 28 A THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78 package, in free air SOT404 & SOT428 packages, pcb mounted, minimum footprint TYP. MAX. UNIT 60 50 1.4 K/W K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 175˚C Tj = -55˚C Drain-source on-state VGS = 10 V; ID = 14 A resistance Gate source leakage current VGS = ± 20 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance Tj = 175˚C Tj = 175˚C MIN. 100 89 2 1 TYP. MAX. UNIT 3 40 10 0.05 30 6 12 12 43 32 24 3.5 4.5 7.5 1240 172 100 4 6 50 135 100 10 500 V V V V V mΩ mΩ nA µA µA nC nC nC ns ns ns ns nH nH nH pF pF pF ID = 27 A; VDD = 80 V; VGS = 10 V VDD = 50 V; RD = 1.8 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load Measured tab to centre of die Measured from drain lead to centre of die (SOT78 package only) Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz August 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS™ transistor PHP27NQ10T, PHB27NQ10T PHD27NQ10T REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS MIN. IF = 14 A; VGS = 0 V IF = 14 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V TYP. MAX. UNIT 0.9 60 160 28 112 1.2 A A V ns nC August 1999 3 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOS™ transistor PHP27NQ10T, PHB27NQ10T PHD27NQ10T Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 10 Transient thermal impedance, Zth j-mb (K/W) 1 D = 0.5 0.2 0.1 0.05 0.02 single pulse T 1E-04 1E-03 1E-02 1E-01 1E+00 P D 0.1 tp D = tp/T 0.01 1E-06 1E-05 Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Drain Current, ID (A) VGS = 10V 8V 6V Tj = 25 C Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175 20 18 16 14 12 10 8 6 4 2 0 0 5V 4.8 V 4.6 V 4.4 V 4.2 V 4V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚.


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