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MA31751 Dataheets PDF



Part Number MA31751
Manufacturers Dynex
Logo Dynex
Description Memory Management & Block Protection Unit
Datasheet MA31751 DatasheetMA31751 Datasheet (PDF)

MA31751 MA31751 Memory Management & Block Protection Unit Replaces June 1999 version, DS4083-2.0 DS4083-3.0 January 2000 The MA31751 Memory Management Unit/Block Protect Unit (MMU/BPU) is an optional chip which may be used to expand the capabilities of the MA31750. User configurable, the MA31751 can perform as an MMU, a BPU or both MMU and BPU, conforming to MIL-STD-1750A and 1750B. MMU mapping and BPU protection for 1M words of memory is provided by the internal memory. Up to 16 MA31751 devic.

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MA31751 MA31751 Memory Management & Block Protection Unit Replaces June 1999 version, DS4083-2.0 DS4083-3.0 January 2000 The MA31751 Memory Management Unit/Block Protect Unit (MMU/BPU) is an optional chip which may be used to expand the capabilities of the MA31750. User configurable, the MA31751 can perform as an MMU, a BPU or both MMU and BPU, conforming to MIL-STD-1750A and 1750B. MMU mapping and BPU protection for 1M words of memory is provided by the internal memory. Up to 16 MA31751 devices can be used to give 16M words of logical mapped onto 8M words of physical address space with protection in 1750B mode. The MA31751 is designed to have a simple interface to both the CPU and the system bus with the minimal number of control lines. This reduces board space and simplifies system design. The MA31751 traps the MMU and BPU XIO commands to program and read the logical to physical mapping and memory access control. This provides simple memory management as defined by the MIL-STD-1750. CPU Busses A[0:15] AS[0:3] PS[0:3] D[0:16] Bus Control OIN MION RDWN ASIN DSN PRPEN MPROEN GLPE System Faults Chip Control Signals DMAKN CSN HITMISSN BPUVALIDN EAS EA[0:10] FEATURES s MlL-STD-1750A/B Compatible s Radiation Hard CMOS/SOS Technology s User Configurable as Either a Memory Management Unit (MMU) or a Block Protect Unit (BPU) or Both s Memory Management Unit Configuration • 1 MWord Physical Address Space • Access Lock and Key of 4K-Word Blocks • Write/Execute Protection of 4K-Word Blocks s Block Protect Unit Configuration • Protection of 1K-Word Blocks • Global Memory Write Protection During Initialisation s Direct Memory Access Support System Signals RESETN VDD GND MA31751 Figure 1: Chip Control Signals 1/17 MA31751 1.0 DEVICE OPERATION The MA31751 is an interface device designed to increase the memory addressing capability of the MA31750 CPU. It is user configurable as an MMU and/or a BPU conforming to the MIL-STD-1750A and the proposed MIL-STD-1750B. The MMU provides expanded addressing and full access lock/key protection in both modes, together with write/execute protection on 4K pages. The BPU allows up to 1M words of memory to be protected in 1K blocks (MlL-STD-1750A). Up to 8M words may be protected by multiple MMU/BPU units (draft MIL-STD-1750B). In 1750A mode, one MA31751 unit can act as both MMU and BPU for the maximum 1M words of address space. In 1750B mode, up to 8 MA31751 units may be used to provide the maximum BPU functions and up to 16 units for the maximum MMU functions. For any given physical memory location the MMU and BPU function may be split across two MA31751 devices depending on the logical to physical address mapping. Figure 2 illustrates the Access Key mapping mechanism. When memory transactions are controlled by the MA31750, the AS[0:3] and PS[0:3] bits necessary to perform the address translation and access protection functions respectively, are obtained from a copy of the processor status word held by the MM.


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