PHD12N10E

Philips Semiconductors Product Specification PowerMOS transistor PHD12N10E GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic envelope suitable for surface mounting. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in general purpose switching applications. QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance MAX. 100 14 75 175 0.16 UNIT V A W ˚C Ω PINNING - SOT428 PIN 1 2 3 tab gate drain source DESCRIPTION PIN CONFIGURATION tab SYMBOL d g 2 drain 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR ±VGS ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction Temperature CONDITIONS RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 100 100 30 14 10 56 75 175 175 UNIT V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum footprint 50 MAX. 2 UNIT K/W K/W September 1997 1 Rev 1.000 Philips Semiconductors Product Specification PowerMOS transis...