PHD21N06LT

Philips Semiconductors Product specification N-channel TrenchMOS™ transistor Logic level FET FEATURES ’Trench’ technology Low on-state resistance Fast switching Logic level compatible g PHP21N06LT, PHB21N06LT PHD21N06LT QUICK REFERENCE DATA d SYMBOL VDSS = 55 V ID = 19 A RDS(ON) ≤ 75 mΩ (VGS = 5 V) RDS(ON) ≤ 70 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. Applications: d.c. to d.c. converters switched mode power supplies The PHP21N06LT is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB21N06LT is supplied in the SOT404 (D2PAK) surface mounting package. The PHD21N06LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain 1 source SOT78 (TO220AB) tab SOT404 (D2PAK) tab SOT428 (DPAK) tab 2 1 23 2 1 3 1 3 drain LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS VGSM ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Pulsed gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tj ≤ 150˚C Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 55 55 ± 15 ± 20 19 13 76 56 175 UNIT V V V V A A A W ˚C 1 It is not possible to make c...