PHD24N03LT

Philips Semiconductors Preliminary specification TrenchMOS transistor Logic level FET FEATURES ’Trench’ technology Very low on-state resistance Fast switching Stable off-state characteristics High thermal cycling performance Low thermal resistance PHD24N03LT SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 24 A g RDS(ON) ≤ 56 mΩ (VGS = 5 V) RDS(ON) ≤ 50 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHD24N03LT is supplied in the SOT428 (DPAK) surface mounting package. PINNING PIN 1 2 3 tab gate drain 1 source DESCRIPTION SOT428 (DPAK) tab 2 drain 1 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 30 30 ± 13 24 20 96 60 175 UNIT V V V A A A W ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. pcb mounted, minimum foo...