MACH120-12

1 FINAL MACH 1 & 2 FAMILIES COM’L: -12/15 IND: -18 Lattice Semiconductor MACH120-12/15 High-Performance EE CMOS Programmable Logic MACH 1 & 2 Families DISTINCTIVE CHARACTERISTICS x 68 Pins in PLCC x 48 Macrocells x 12 ns tPD Commercial, 18 ns tPD Industrial x x x x x x x 77 MHz fCNT Commercial 48 I/Os; 4 dedicated inputs; 4 dedicated inputs/clocks 48 Outputs 48 Flip-flops; 4 clock choices 4 “PALCE26V12” blocks SpeedLocking™ for guaranteed fixed timing Pin-compatible with the MACH221 GENERAL DESCRIPTION The MACH120 is a member of the high-performance EE CMOS MACH ® 1 family. This device has approximately five times the logic macrocell capability of the popular PALCE22V10 without loss of speed. The MACH120 consists of four PAL® blocks interconnected by a programmable switch matrix. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH120 macrocell provides either registered or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use a...