Document
FINAL
COM’L: -7/10/12/15/20, Q-12/15/20
IND: -12/14/18/24
MACH210A-7/10/12 MACH210-12/15/20 MACH210AQ-12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
44 Pins 64 Macrocells 7.5 ns tPD Commercial 12 ns tPD Industrial 133 MHz fCNT 38 Inputs; 210A Inputs have built-in pull-up resistors
Advanced Micro Devices
Peripheral Component Interconnect (PCI) compliant 32 Outputs 64 Flip-flops; 2 clock choices 4 “PAL22V16” blocks with buried macrocells Pin-compatible with MACH110, MACH111, MACH211, and MACH215
GENERAL DESCRIPTION
The MACH210 is a member of AMD’s high-performance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macrocells, including additional buried macrocells. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH210 has two kinds of macrocell: output and buried. The MACH210 output macrocell provides registered, latched, or combinatorial outputs with programmable polarity. If a registered configuration is chosen, the register can be configured as D-type or T-type to help reduce the number of product terms. The register type decision can be made by the designer or by the software. All output macrocells can be connected to an I/O cell. If a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the I/O pin for use as an input. The MACH210 has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements.
Publication# 14128 Rev. I Issue Date: May 1995
Amendment /0
AMD
BLOCK DIAGRAM
I0–I1, I3–I4 8 I/O Cells 8 Macrocells
OE
I/O0–I/O7 8 I/O Cells 8 Macrocells 8
I/O8–I/O15
8 8 Macrocells
OE
8 Macrocells
2
44 x 68 AND Logic Array and Logic Allocator 22
44 x 68 AND Logic Array and Logic Allocator 22
4
Switch Matrix 22 44 x 68 AND Logic Array and Logic Allocator
OE
22 44 x 68 AND Logic Array and Logic Allocator
OE
2
Macrocells 8 I/O Cells 8 8
Macrocells 8
Macrocells 8 I/O Cells 8 8
Macrocells 8
2
I/O24–I/O31
I/O16–I/O23
CLK0/I2, CLK1/I5
14128I-1
2
MACH210-7/10/12/15/20, Q-12/15/20
AMD
CONNECTION DIAGRAM Top View PLCC
I/O31 I/O30 I/O2 I/O1 VCC I/O29 I/O28 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 I/O14 I/O15 GND I/O18 I/O19 VCC I/O12 I/O13 I/O16 I/O17 I/O20 I/O0 GND 2 I/O4 6 I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11 7 8 9 10 11 12 13 14 15 16 17 I/O3 5
4
3
1 44 43 42 41 40 I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21
14128I-2
Note: Pin-compatible with MACH110, MACH111, MACH211, and MACH215.
MACH210-7/10/12/15/20, Q-12/15/20
3
AMD
CONNECTION DIAGRAM Top View TQFP
I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
I/O5 I/O6 I/O7 I0 I1 GND CLK0/I2 I/O8 I/O9 I/O10 I/O11
33 32 31 30 29 28 27 26 25 24 23
I/O27 I/O26 I/O25 I/O24 CLK1/I5 GND I4 I3 I/O23 I/O22 I/O21
I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20
Note: Pin-compatible with MACH111 and MACH211.
14128I-3
PIN DESIGNATIONS
CLK/I = GND I I/O VCC = = = = Clock or Input Ground Input Input/Output Supply Voltage
4
MACH210-7/10/12/15/20, Q-12/15/20
AMD
ORDERING INFORMATION Commercial Products
AMD programmable logic products for commercial applications are available with several ordering options. The order number (Valid Combination) is formed by a combination of:
MACH
210A -7
J
C
FAMILY TYPE MACH = Macro Array CMOS High-Speed DEVICE NUMBER 210 = 64 Macrocells, 44 Pins 210A = 64 Macrocells, 44 Pins, Input Pull-Up Resistors 210AQ = 64 Macrocells, 44 Pins, Input Pull-Up Resistors, Quarter Power SPEED -7 = 7.5 ns tPD -10 = 10 ns tPD -12 = 12 ns tPD -15 = 15 ns tPD -20 = 20 ns tPD Valid Combinations MACH210A-7 MACH210A-10 MACH210A-12 MACH210-12 MACH210-15 MACH210-20 MACH210AQ-12 MACH210AQ-15 MACH210AQ-20 JC, VC
OPTIONAL PROCESSING Blank = Standard Processing
OPERATING CONDITIONS C = Commercial (0°C to +70°C) PACKAGE TYPE J = 44-Pin Plastic Leaded Chip Carrier (PL 044) V = 44-Pin Thin Quad Flat Pack (PQT044)
Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations or to check on newly released combinations.
JC
MACH210-7/10/12/15/20, Q-12/15/20 (Com’l)
5
AMD
ORDERING INFORMATION Industrial Products
AMD programmable logic products for.