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MACH215-12

Lattice

High-Density EE CMOS Programmable Logic

FINAL COM’L: -12/15/20 IND: -14/18/24 MACH215-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERI...


Lattice

MACH215-12

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Description
FINAL COM’L: -12/15/20 IND: -14/18/24 MACH215-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s s s s 44 Pins 32 Output Macrocells 32 Input Macrocells Product terms for: — Individual flip-flop clock — Individual asynchronous reset, preset — Individual output enable 12 ns tPD Commercial 14.5 ns tPD Industrial 67 MHz fCNT s s s s s s Lattice Semiconductor 38 Inputs with pull-up resistors 32 Outputs 64 Flip-flops For asynchronous and synchronous applications 4 “PAL22RA8” blocks with buried macrocells Pin-compatible with MACH110, MACH111, MACH210, and MACH211 s s GENERAL DESCRIPTION The MACH215 is a member of the high-performance EE CMOS MACH device family. This device has approximately three times the capability of the popular PAL20RA10 without loss of speed. This device is designed for use in asynchronous as well as synchronous applications. The MACH215 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are essentially “PAL22RA8” structures complete with product-term arrays and programmable macrocells, individual register control product terms, and input registers. The switch matrix connects the PAL blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected PAL blocks. This allows designs to be placed and routed efficiently. The MACH215 has two kinds of macrocell: output and input. The MACH215 output macrocell provides registered, latched, or com...




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