MACHLV210-12

FINAL COM’L: -12/15/20 IND: -18/24 MACHLV210-12/15/20 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s Low-voltage operation, 3.3-V JEDEC compatible — VCC = +3.0 V to +3.6 V s < 5 mA standby current s Patented design allows minimal standby current without speed degradation s Exclusively designed for 3.3-V applications s 44 Pins s 64 Macrocells s 12 ns tPD Commercial 18 ns tPD Industrial s 83.3 MHz fCNT Lattice Semiconductor s 38 Bus-Friendly Inputs s 32 Outputs s 64 Flip-flops; 2 clock choices s 4 “PAL22V16” blocks with buried macrocells s Pin-, function-, and JEDEC-compatible with MACH210 s Pin-compatible with MACH110, MACH111, MACH210, MACH211, and MACH215 GENERAL DESCRIPTION The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family. This device has approximately six times the logic macrocell capability of the popular PAL22V10 at an equal speed with a lower cost per macrocell. It is architecturally identical to the MACH210, with the addition of I/O pull-up/pull-down resistors and low-voltage, low-power operation. The MACHLV210 provides 3.3-V operation with lowpower CMOS technology. The patented design allows for minimal standby current without speed degradation by limiting the leakage current when signals are not switching. At less than 5 mA maximum standby current, the MACHLV210 is ideal for low-power applications. The MACHLV210 consists of four PAL blocks interconnected by a programmable switch matrix. The four PAL blocks are...