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PHK5NQ10T Dataheets PDF



Part Number PHK5NQ10T
Manufacturers NXP
Logo NXP
Description N-channel TrenchMOS transistor
Datasheet PHK5NQ10T DatasheetPHK5NQ10T Datasheet (PDF)

Philips Semiconductors Product specification N-channel TrenchMOSTM transistor PHK5NQ10T FEATURES • Low on-state resistance • Fast switching • Low profile surface mount package SYMBOL d QUICK REFERENCE DATA VDS = 100 V ID = 5 A g RDS(ON) ≤ 50 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode field-effect transistor in a plastic envelope using ’trench’ technology. Applications:• Motor and relay drivers • d.c. to d.c. converters The PHK5NQ10T is supplied in the SOT96-1 (SO8) .

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Philips Semiconductors Product specification N-channel TrenchMOSTM transistor PHK5NQ10T FEATURES • Low on-state resistance • Fast switching • Low profile surface mount package SYMBOL d QUICK REFERENCE DATA VDS = 100 V ID = 5 A g RDS(ON) ≤ 50 mΩ (VGS = 10 V) s GENERAL DESCRIPTION N-channel enhancement mode field-effect transistor in a plastic envelope using ’trench’ technology. Applications:• Motor and relay drivers • d.c. to d.c. converters The PHK5NQ10T is supplied in the SOT96-1 (SO8) surface mounting package. PINNING PIN 1-3 4 5-8 DESCRIPTION source gate drain SOT96-1 (SO8) 8 7 6 5 pin 1 index 1 2 3 4 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDSS VDGR VGS ID IDM Ptot Tj, Tstg PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Drain current (tp ≤ 10 s) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Ta = 25 ˚C Ta = 70 ˚C Ta = 25 ˚C Ta = 25 ˚C, t ≤ 10 s Ta = 70 ˚C, t ≤ 10 s MIN. - 65 MAX. 100 100 ± 20 5 3.6 20 2.5 1.6 150 UNIT V V V A A A W W ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted, FR4 board, t ≤ 10 sec Surface mounted, FR4 board TYP. 150 MAX. 50 UNIT K/W K/W August 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOSTM transistor PHK5NQ10T ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 10 µA; Tj = -55˚C VDS = VGS; ID = 1 mA Tj = 150˚C Tj = -55˚C Drain-source on-state VGS = 10 V; ID = 5 A resistance Gate source leakage current VGS = ±20 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 5 A; VDD = 80 V; VGS = 10 V Tj = 150˚C Tj = 150˚C MIN. 100 89 2 1.1 TYP. MAX. UNIT 3 40 10 0.05 30 4 11 8 14 35 15 1 3 1240 172 100 4 6 50 120 100 10 100 V V V V V mΩ mΩ nA µA µA nC nC nC ns ns ns ns nH nH pF pF pF VDD = 50 V; RD = 10 Ω; VGS = 10 V; RG = 5.6 Ω Resistive load Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tj = 25˚C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ta = 25 ˚C, tp ≤ 10 s MIN. IF = 5 A; VGS = 0 V IF = 5 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 25 V TYP. MAX. UNIT 0.82 65 100 2.3 18 1.2 A A V ns nC August 1999 2 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOSTM transistor PHK5NQ10T Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 Ambient temperature, Ta (C) 125 150 100 Transient thermal impedance, Zth j-a (K/W) D = 0.5 0.2 10 0.1 0.05 1 0.02 single pulse 0.1 T 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01 P D D = tp/T tp Pulse width, tp (s) Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ta) Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T Drain Current, ID (A) VGS = 10V 8V 6V Tj = 25 C Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 Ambient temperature, Ta (C) 125 150 20 18 16 14 12 10 8 6 4 2 0 0 5V 4.8 V 4.6 V 4.4 V 4.2 V 4V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ta); VGS ≥ 10 V Peak Pulsed Drain Current, IDM (A) Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS) 100 0.2 RDS(on) = VDS/ ID 10 tp = 10 us 100 us 1 ms 1 D.C. 0.1 10 ms 100 ms 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0.01 0.1 1 10 100 Drain-Source Voltage, VDS (V) 1000 0 Drain-Source On Resistance, RDS(on) (Ohms) 4.2 4.4 4.6 4.8 5V Tj = 25 C 8V 6V VGS = 10V 0 2 4 6 8 10 12 Drain Current, ID (A) 14 16 18 20 Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID) August 1999 3 Rev 1.000 Philips Semiconductors Product specification N-channel TrenchMOSTM transistor PHK5NQ10T Drain current, ID (A) 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 Gate-source voltage, VGS (V) 150 C Tj = 25 C VDS > ID X RDS(ON) 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 Threshold Voltage, VGS(TO) (V) maximum typical minimum -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction Temper.


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