PHN1015

Philips Semiconductors Product specification N-channel TrenchMOS transistor Logic level FEATURES ’Trench’ technology Low on-state resistance Fast switching Low-profile surface mount package Logic level compatible PHN1015 SYMBOL d QUICK REFERENCE DATA VDSS = 25 V ID = 10 A g RDS(ON) ≤ 15 mΩ (VGS = 10 V) RDS(ON) ≤ 18 mΩ (VGS = 5 V) s GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a surface mounting plastic package using ’trench’ technology. Application: High frequency computer motherboard d.c. to d.c. converters The PHN1015 is supplied in the SOT96-1 (SO8) surface mounting package. PINNING PIN 1-3 4 5-8 DESCRIPTION source gate drain SOT96-1 (SO8) 8 7 6 5 pin 1 index 1 2 3 4 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDSS VDGR VGS VGSM ID IDM Ptot Tj, Tstg PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage (DC) Gate-source voltage (pulse peak value) Drain current (tp ≤ 10 s) Drain current (pulse peak value) Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Ta = 25 ˚C Ta = 70 ˚C Ta = 25 ˚C Ta = 25 ˚C Ta = 70 ˚C MIN. - 55 MAX. 25 25 ± 15 ± 20 10 8 40 2.5 1.6 150 UNIT V V V V A A A W W ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted, FR4 board, t ≤ ...